Signetics 2650 microprocessor architecture

  Memory  

Program instructions and data are located in the same memory space. The total addressable memory size is 32 KB.

Program memory - program instructions can be located anywhere in memory. All branch instructions, which use absolute addressing and indirect relative addressing, can jump to any location in program memory. Branch instructions that use relative non-indirect addressing can jump up to +63/-64 bytes from the address of the next instruction.

Data memory - program data can be located anywhere in memory. All instructions that use indirect addressing method can access data placed anywhere. Instructions that don't use indirect memory addressing can only access data within current 8 KB memory page.

Stack memory is located on the CPU. Stack size is 8 x 15 bits, that is it can store 8 return addresses. Stack cannot be used to store program data.

Reserved/Special locations:

• 0000h - The CPU jumps to this location after reset.
• 0000h - 003Fh, 1FC0h - 1FFFh - First and last 64 bytes in a zero memory page can be used for interrupt handling routines or vectors to them.

  Interrupts  

The processor supports only one type of interrupt. When an external device generates interrupt signal, the CPU finishes processing of current instruction, sets Interrupt Inhibit bit in the Program Status Word register and starts executing ZBSR instruction (branch to subroutine with the address relative to page zero). Second byte of the ZBSR instruction is supplied by the external device. This byte specifies memory location, relative to byte 0 in zero page, where the interrupt handling routine or a vector to it is located. The CPU stores the address of next instruction in stack memory, and jumps to the interrupt handling routine. When the routine finishes processing the interrupt, it can execute RETE instruction, which clears II flag, or it may choose to clear II flag first and then execute RETC instruction.

Interrupts can be enabled or disabled by clearing/setting II (Interrupt Inhibit) flag.

  I/O ports  

256 8-bit ports. Single-bit I/O port

  Registers  

Program Status Word register - 16-bit register containing the following status and control bits:

• Carry (C, bit 0). This bit can be set:
  • If there was a carry during previous addition operation.
  • If there was no borrow during previous subtraction operation.
  • If 0th or 7th bit of the operand was set during previous right or left rotate operation, and the WC flag was set to 1.
• Compare (COM, bit 1). This flag modifies behavior of COMPARE instruction. When the flag is set the COMPARE instruction compares operands as arithmetic numbers, i.e. it compares operands as signed numbers. When the flag is cleared then COMPARE instruction compares 8-bit operands as unsigned (positive) numbers.
• Overflow (OVF, bit 2). This flag is set when addition or subtraction results in a too large positive number, or a too small negative number, that cannot fit into into one byte, that is if the result is greater than +127 or smaller than -128. For example, adding 100 and 100 will set the overflow flag. The flag can be also set by rotate instructions when the result has different sign than the original operand.
• With Carry (WC, bit 3). This bit modifies behavior of add, subtract and rotate instructions. When this bit is set, the add and subtract instructions will utilize carry bit in their calculations, and rotate instructions will rotate 8-bit data through the carry. When the flag is cleared, the add and subtract instructions do not use the carry bit, and rotate instructions rotate only 8 bits of data.
• Register Select (RS, bit 4). This flag controls which bank of registers (registers 1, 2 and 3) is currently used.
• Inter Digit Carry (IDC, bit 5). This flag is set when there was a carry from or borrow out of bit 3 during last arithmetic operation. When the WC flag is set, rotate instructions will also set this flag - it will be the same as 5th bit of the result.
• Condition Code (CC, bits 6 and 7). CC flags are when the CPU executes COMPARE instruction to compare two operands. This flags can be also set after load and other arithmetic operations - in this case the CPU compares the loaded/calculated value with 0, and sets the flags accordingly. Possible values are:
  • 0 - the first operand is the same as the second operand.
  • 1 - the first operand is grater than the second operand.
  • 2 - the first operand is less than the second operand.
  For loaded/calculated values, when the second operand is zero, the possible values are the same as:
  • 0 - loaded/calculated result is zero.
  • 1 - the result is positive.
  • 2 - the result is negative.
• Stack Pointer (SP, bits 8, 9 and 10). This 3-bit number specifies position of current return address in the stack. When the CPU jumps to a subroutine, it increments the stack pointer and stores the address of next instruction in the stack. The stack pointer is automatically decremented when the CPU executes RETE or RETC instruction.
• Interrupt Inhibit (II, bit 13). When set, this flag disables all further interrupts. The CPU automatically sets this bit to 1 every time it processes external interrupts. Clearing this flag enables interrupts.
• Flag (F, bit 14). This control bit drives pin #40 of the CPU. Together with S flag, it can be used for simple serial I/O communications, or for other applications.
• Sense (S, bit 15). This bit contains the state of pin #1 of the CPU. The S bit cannot be set or cleared by program.

General registers:
The CPU has 7 general 8-bit registers, but only 4 of them can be accessed at any given time - these are referred to as registers 0, 1, 2 and 3. Three additional general registers are organized as the second bank of registers. These registers replace registers 1, 2 and 3 when a program sets a flag RS in the program status word. The program can switch back to original registers 1, 2 and 3 at any time by clearing the RS flag. All registers can be used for arithmetic and logical operations, and for indexed addressing modes.

  Instruction Set  

2650 instruction set consists of the following instructions:

• Load/Store instructions.
• Arithmetic - add, subtract and compare.
• Logical - AND, OR, XOR and rotate.
• Control transfer - conditional and unconditional branch to memory location or to a subroutine, return from subroutine.
• Input/Output instructions.
• Other - setting/clearing Program Status Word, Halt and NOP.

  Addressing modes  

Register - references data in a register.

Immediate - 8-bit data is provided in the instruction.

Absolute - two-byte operand provided in the instruction specifies memory address in current 8 KB page (for non-branch instruction) or in memory (for branch instructions) where data is located.

Absolute Indirect - two-byte operand provided in the instruction specifies memory address in current 8 KB page where 16-bit data address is stored.

Absolute indexed - the contents of one general register is added to two-byte operand provided in the instruction. The resulting address points to memory where data is located.

Absolute indexed with auto-increment - the contents of one general register is incremented, and then added to two-byte operand provided in the instruction. The resulting address points to memory where data is located.

Absolute indexed with auto-decrement - the contents of one general register is decremented, and then added to two-byte operand provided in the instruction. The resulting address points to memory where data is located.

Relative - 7-bit offset, provided in the second byte of the instruction, is added to the address of the next instruction. The offset is a signed number in the range -64 - +63.

Zero Page Relative - 7-bit offset, provided in the second byte of the instruction, specifies memory location in the zero page (first 8 KB page) where data is located. The offset is a signed number in the range -64 - +63, so this addressing method can access memory locations 0000h - 003Fh and 1FC0h - 1FFFh.

Relative Indirect - 7-bit offset (signed number in the range -64 - +63), provided in the second byte of the instruction, is added to the address of the next instruction. The calculated address points to memory location where 16-bit data address is stored.

Zero Page Relative Indirect - 7-bit offset, provided in the second byte of the instruction, specifies memory location in the zero page (first 8 KB page) which contains 16-bit data address.