Intel 4040 microprocessor architecture
Program memory size is 8 KB organized as two 4 KB memory banks. At any point of time the processor works with one 4 KB bank, when necessary the processor can switch to different bank using new DB0 and DB1 instructions. Like in Intel 4004, all conditional instructions in the 4040 work within currently selected ROM (256 bytes). Unconditional jump and jump to subroutine instructions can be used to jump to any address within currently selected bank.
Data memory size is 640 bytes. RAM access is done in the same way as access to I/O ports. First, a SRC instruction is used to tell the processor what memory address to access, and successive WRM or RDM writes accumulator data to memory or reads data into accumulator. Data memory is separate from program memory.
Stack is 7-level deep. Stack is separate from program memory and data memory.
The processor has one maskable interrupt. The interrupt can be disabled or enabled using DIN and EIN instructions. When interrupt occurs, the contents of the program counter and the send register (SRC) is preserved. To return from the interrupt the interrupt processing code should execute BBS instruction.
16 4-bit input ports.
Program counter (12-bit).
Stack registers. There are seven stack level registers, which is sufficient to implement 7-level deep subroutine calls. Every subroutine call stores return address in one of the stack registers. Contents of the accumulator and the index registers is not preserved. When the program is interrupted, the contents of the send register (SRC) is also preserved in the stack.
Accumulator (4-bit). Mainly used for arithmetic and logic operations, as well as for reading and writing data from/to RAM and I/O ports.
Index registers. The microprocessor has 24 4-bit registers, organized as 16 registers in bank 0 and 8 registers in bank 1. Lower 8 registers can be selected from bank 0 or 1 using SB0 and SB1 instructions. The registers can work in pairs as 8 8-bit registers.
4040 instruction set consists of 60 instructions:
Instruction length can be one or two bytes.
Register indirect. Register indirect can access data only within current ROM.
Immediate (4 and 8-bit data).
Jump to CPU / Family