Intersil 6100 microprocessor architecture

Memory

Program memory and data memory occupy the same memory space. The total size of directly addressable memory is 4 K words. Word size is 12 bits. The 6100 doesn't have stack memory.

Program memory size is 4 K words. All conditional instructions allow the processor to skip the next instruction only. To go conditionally to arbitrary address in memory when certain condition is met the code should execute "skip if the condition is not met" instruction first and put direct or indirect unconditional jump instruction after the skip instruction. Unconditional instructions can be used to jump directly within current page (127 words), or jump indirectly within the whole memory space (4 K words). The 6100 supports subroutine calls, but, due to lack of stack memory, the return address for subroutines is stored in memory. There is no "return from subroutine" instruction - the subroutine should use indirect jump to return back to the caller.

Data memory size is 4 K words. The data can be accessed directly within zero page (0000h - 007Fh) or within current 127-word page. The data can be accessed indirectly anywhere in 4 K words of memory.

Reserved locations:

  • 0000h - This memory location is used to store the contents of program counter when the interrupt occurs.
  • 0001h - This location contains address of interrupt handling routine.
  • 0008h - 000Fh - Autoindexed memory locations. When any instruction uses indirect addressing to access addresses stored in one of these memory locations, the contents of accessed memory location (i.e. the stored address) is incremented by one afterwards.

Interrupts

The processor has one maskable interrupt. The interrupt can be disabled or enabled using IOF and ION (or SKON) instructions. When interrupt occurs, the contents of the program counter is stored in memory location 0000h, further interrupts are disabled and the control is transferred to interrupt handling routing the address of which is stored in memory location 0001h. To return from the interrupt the interrupt processing code should execute ION and JMP I 0000 instructions (indirect jump using absolute location 0000h).

I/O ports

64 I/O ports (devices).

Registers

Program counter (12-bit). Points to memory location from which the next instruction will be fetched. Also, upper five bits of program counter specify current 127-word page. For example, if program counter contains address 0456h then the current page location is 0400h.

Accumulator (12-bit). The Accumulator is used for arithmetic and logical operations, loading and saving data from/to memory, and for I/O operations.

Link (1-bit). The Link register is set if there was a carry from the most significant bit during last addition. The Link is also changed by RAL, RTL, RAR and RTR instructions, i.e. when the contents of the accumulator and the link register is rotated to the left or the right. The processor has special instructions to set and clear the link value, as well as check for it, so this register may be used as a flag.

MQ (12-bit). This register is used as a temporary storage.

Instruction Set

6100 instruction set consists of the following instructions:

Memory referencing instructions - these instructions include unconditional jumps to memory and subroutine, and accumulator-related instructions: add, increment, logical AND and store. There is no "load from memory" instruction. Instead, the code would clear the accumulator and use add instruction to effectively load data from memory.

Operate instructions - these consist of three groups of instructions listed below. Each group includes a few microinstructions. The microinstructions are different from other instructions in the way that multiple microinstructions from the same group can be combined together into one instruction. This is accomplished by reserving a part of the instruction word for microinstruction use, and using separate bits in this reserved part to encode different microinstructions. As a result, it becomes possible to use logical OR to combine microinstruction bits and thus create a new instruction.

  • Group 1 - clear, rotate or complement accumulator. Clear, set or complement the link.
  • Group 2 - Skip instructions. The next instruction is skipped when certain condition or combination of conditions is/are met.
  • Group 2 - MQ register instructions. Load and clear MQ register, or swap it with the accumulator.

Input/Output transfer - load from and store to I/O device, perform logical OR of the accumulator and I/O device data, load or add to program counter from I/O device.

Instruction length is always 1 word (12 bits).

Addressing modes

Accumulator - references data in accumulator.

Direct - the instruction contains memory offset within current 127-word page.

Zero page direct - the instruction contains memory offset within zero page (0000h - 0007Fh).

Indirect - the instruction contains the memory offset within current page where data address is stored.

Zero page indirect - the instruction contains the memory offset within zero page where data address is stored. Memory offset cannot be in the range of 0008h - 000Fh.

Autoindexed indirect - the instruction contains the memory offset within zero page where data address is stored. After the data address is used to access the data, the data address in memory is incremented. Memory offset must in in the range of 0008h - 000Fh.

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Last modified: 15 Oct 2013
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