Motorola 6809 microprocessor architecture

Memory

Program, data and stack memories occupy the same memory space. The total addressable memory size is 64 KB.

Program memory - program can be located anywhere in memory. Jump, subroutine calls and conditional branches instructions can be used to jump anywhere in memory.

Data memory - data can be anywhere in memory space.

Stack memory - user and system stacks can be placed anywhere in memory space. Stacks grow downwards.

Reserved memory locations:

  • FFF0h - FFF1h: reserved for future use.
  • FFF2h - FFF3h: Pointer to SWI3 interrupt-processing routine.
  • FFF4h - FFF5h: Pointer to SWI2 interrupt-processing routine.
  • FFF6h - FFF7h: Pointer to FIRQ interrupt-processing routine.
  • FFF8h - FFF9h: Pointer to IRQ interrupt-processing routine.
  • FFFAh - FFFBh: Pointer to SWI interrupt-processing routine.
  • FFFCh - FFFDh: Pointer to NMI interrupt-processing routine.
  • FFFEh - FFFFh: Pointer to RESET handling code.
  • Because the processor doesn't have hardware I/O capability some memory addresses may be reserved for memory mapped I/O.

Interrupts

IRQ - maskable interrupt. When the interrupt occurs the CPU sets E condition flag, pushes program counter, index registers, accumulators and condition code register into the stack, disables further IRQ interrupts by setting I condition flag, and jumps to memory location, address of which is stored in memory FFF8h - FFF9h. To return from the interrupt the processing routine should use RTI instruction. This interrupt can be enabled/disabled by setting/clearing I condition flag.

FIRQ - fast maskable interrupt. When the interrupt occurs the CPU clears E condition flag, pushes program counter and condition code register into the system stack, disables further fast and normal interrupts by setting I and F condition flags, and jumps to memory location, address of which is stored in memory FFF6h - FFF7h. To return from the interrupt the processing routine should use RTI instruction. This interrupt can be enabled/disabled by setting/clearing F condition flag. FIRQ interrupt has higher priority than IRQ.

NMI - non-maskable interrupt. When the interrupt occurs the CPU clears E condition flag, pushes program counter, index registers, accumulators and condition code register into the system stack, disables further maskable interrupts by setting F and I condition flags, and jumps to memory location, address of which is stored in memory FFFCh - FFFDh. To return from the interrupt the processing routine should use RTI instruction. NMI interrupt has higher priority than IRQ and FIRQ interrupts. This interrupt can not be disabled.

SWI - software interrupt. This interrupt can be only invoked from the program. When the interrupt is invoked the CPU sets E condition flag, pushes program counter, index registers, accumulators and condition code register into the system stack, disables maskable interrupts by setting F and I condition flags, and jumps to memory location, address of which is stored in memory FFFAh - FFFBh. To return from the interrupt the processing routine should use RTI instruction.

SWI2 - software interrupt 2. This interrupt can be only invoked from the program. When the interrupt is invoked the CPU sets E condition flag, pushes program counter, index registers, accumulators and condition code register into the system stack, and jumps to memory location, address of which is stored in memory FFF4h - FFF5h. To return from the interrupt the processing routine should use RTI instruction.

SWI3 - software interrupt 3. This interrupt works almost like SWI2 with the only exception that the address of SWI3 interrupt processing routine is located at FFF2h - FFF3h.

I/O ports

None.

Registers

Accumulator A (A) is an 8-bit register used for arithmetic and logical operations.

Accumulator B (A) is an 8-bit register used for arithmetic and logical operations. Most instructions that work with the accumulator A can be used with the accumulator B. The only exceptions are instructions DAA (works with the accumulator A only) and ABX (works with the accumulator B only).

Accumulators A and B can be combined together into 16-bit accumulator D. The register A contains the most significant byte of the accumulator D, and the register B contains the least significant byte.

Index registers X and Y are a 16-bit registers that usually contain an index used for indexed addressing modes.

Program counter (PC) is a 16-bit register pointing to the next instruction that will be executed by the CPU. PC register can be used with some indexed addressing modes.

System stack pointer (S) is a 16-bit register pointing to the top of system stack. The system stack stores machine state during subroutine calls and interrupts.

User stack pointer (U) is a 16-bit register pointing to the top of user stack. The user stack is usually used to pass arguments to/from subroutines, and it can also be used for temporary data storage.

When data is pushed into the system or user stack, a stack register is decremented by 2 and then data is stored into memory location referenced by the stack pointer.

Both S and U stack registers can be used as index registers.

Direct Page register contains the most significant byte of the zero page address. After CPU reset this register is set to value 00h.

Condition code register contains the following flags:

  • Entire flag (E, bit 7) - set if the complete machine state was saved in the stack. If this bit is not set then only program counter and condition code registers were saved in the stack. This bit is used by interrupt handling routines only. The bit is cleared by fast interrupts, and set by all other interrupts.
  • Fast interrupt mask (F, bit 6) - set if the FIRQ interrupt is disabled.
  • Half carry (H, bit 5) - set if there was a carry from bit 3 to bit 4 of the result during the last add operation.
  • Interrupt mask (I, bit 4) - set if the IRQ interrupt is disabled.
  • Negative (N, bit 3) - set if the most significant bit of the result is set. This bit can be set not only by arithmetic and logical operations, but also by load/store operations.
  • Zero (Z, bit 2) - set if the result is zero. Like the N bit, this bit can be set not only by arithmetic and logical operations, but also by load/store operations.
  • Overflow (V, bit 1) - set if there was an overflow during last result calculation. Logical, load and store operations clear this bit.
  • Carry (C, bit 0) - set if there was a carry from the bit 7 during last add operation, or if there was a borrow from last subtract operation, or if bit 7 of the A register was set during last MUL operation.

Instruction Set

6800 instruction set consists of 59 instructions:

  • Data moving instructions - load, store, clear and exchange.
  • Arithmetic - add, subtract, negate, increment, decrement, compare, test and multiply.
  • Logic - AND, OR, exclusive OR, complement and shift/rotate.
  • Control transfer - call and return from subroutine, jumps and conditional and unconditional branches.
  • Other - bit test, stack operations, software interrupts, etc.

Addressing modes

Inherent - the data value/data address is implicitly associated with the instruction.

Immediate - 8-bit or 16-bit data is provided in the instruction.

Register - references the data in a register or in a register pair.

Direct - one-byte operand provided in the instruction specifies the memory address in page zero where data is located. Page zero after processor reset always points to 0000h. Zero page address can be changed to any 256-bit page boundary by setting Direct Page register to the high order byte of the page address. For example, to move zero page to memory 8100h the Direct Page register should be set to 81h.

Extended - two-byte operand provided in the instruction specifies memory location where data is stored.

Extended Indirect - two-byte operand provided in the instruction specifies memory location where data address is stored.

Relative - one- or two-byte offset is added to the program counter. The resulting value is a memory address containing data or memory address where the CPU transfers control.

Relative Indirect - one- or two-byte offset is added to the program counter. The resulting value is a memory address where data address is stored.

Indexed - the contents of one of index or pointer registers is added to fixed offset value / content of accumulator register. The resulting value is a memory address where data resides. For indirect indexed modes the calculated address points to memory where data address is stored. The processor supports the following indexed addressing modes:

  • Zero-offset Indexed - the contents of index or pointer register contains memory location where data resides.
  • Zero-offset Indexed Indirect - the contents of index or pointer register contains memory location where data address resides.
  • Constant-offset Indexed - the contents of index or pointer register is added to 5-bit, 8-bit or 16-bit offset value. The resulting value is a memory address where data resides.
  • Constant-offset Indexed Indirect - the contents of index or pointer register is added to 5-bit, 8-bit or 16-bit offset value. The resulting value is a memory address where data address resides.
  • Accumulator-offset Indexed - the contents of index or pointer register is added to the contents of accumulator A or B. The resulting value is a memory address where data resides.
  • Accumulator-offset Indexed Indirect - the contents of index or pointer register is added to the contents of accumulator A or B. The resulting value is a memory address where data address resides.
  • Auto-Increment Indexed - the contents of index or pointer register contains memory location where data resides. After the CPU reads/updates the data the content of index or pointer register is incremented by 1 or 2.
  • Auto-Increment Indexed Indirect - the contents of index or pointer register contains memory location where data address is stored. After the CPU reads the data address and accesses/updates the data, the content of index or pointer register is incremented by 1 or 2.
  • Auto-Decrement Indexed - the content of index or pointer register is decremented by 1 or 2. The resulting register value is memory location where data resides.
  • Auto-Decrement Indexed Indirect - the content of index or pointer register is decremented by 1 or 2. The resulting register value is memory location where data address is stored.
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Last modified: 15 Oct 2013
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