Zilog Z80 microprocessor architecture
In additon to Z80 native instructions the Z80 microprocessor includes as a subset all 8080 instructions. This document describes only Z80 native architecture and instruction set.
Program, data and stack memories occupy the same memory space. The total addressable memory size is 64 KB.
16-bit pointers and data are stored as:
Program memory - program can be located anywhere in memory. Some jump and all call instructions use 16-bit addresses - they can be used to jump anywhere within 64 KB. Some conditional jump instructions can be used to jump within +129 - -126 bytes from the next instruction.
Data memory - the processor can access data anywhere in the memory. Word data can be located at odd or even byte boundaries.
Stack memory can be placed anywhere in memory. The stack grows from the top to bottom.
The processor has the following interrupts:
INT is a maskable hardware interrupt. This interrupt can be enabled/disabled using EI/DI instructions. When an interrupt occurs, then, depending on interrupt mode set in registers IMFa and IMFb, the processor performs the following action:
Interrupt mode can be set using IM 0, IM 1 and IM 2 instructions. RETI instruction is used to return from maskable interrupt.
NMI is a non-maskable interrupt. When non-maskable interrupt occurs the CPU will preserve the content of IFF1 register in IFF2 register, disable maskable interrupts and jump to location 0066h. This interrupt has higher priority then the maskable interrupt. RETN instruction is used to return from non-maskable interrupt.
Software interrupts can be invoked by executing RST0 - RST7 instructions. These interrupts are processed in the same way as hardware mode 0 maskable interrupts.
256 Input ports
Z80 microprocessor has the following registers:
Accumulator (A) register is an 8-bit register used for arithmetic, logic, I/O and load/store operations.
Flag is an 8-bit register containing 6 1-bit flags:
The Z80 CPU includes alternative set of of Accumulator, Flag and General registers. It is not possible to change those registers directly, but it's possible to swap main and alternative registers thus getting access to alternative registers.
Index registers (IX and IY) are used for indexed addressing.
Stack pointer is a 16 bit register. This register points to last used memory location in program stack. The stack pointer is decremented when data is pushed into the stack, and incremented when data is popped from it.
Program Counter (PC) is a 16-bit register. This register contains an address of the next instruction.
Interrupt vector (I) is an 8-bit register. This register contains upper 8-bit of an address where interrupt processing routines or entrance points for interrupt mode 2 are located.
Memory refresh (R) is an 8-bit register. Lower 7 bits of this register are automatically incremented after each instruction fetch and used for dynamic memory refresh. The 8th bit is not used for dynamic refresh. If necessary, the memory refresh register can be set using LD R, A instruction.
Interrupt flip-flop 1 (IFF1) 1-bit register. This register contains 1 if maskable interrupts are enabled, and 0 if maskable interrupts are disabled. When non-maskable interrupt occurs the content of this register is preserved in IFF2 register, and this register is reset to 0.
Interrupt flip-flop 2 (IFF2) 1-bit register. This register is used to store the content of IFF1 register when non-maskable interrupt occurs.
Interrupt mode flip-flops (IMFa and IMFb) are two 1-bit registers.
These registers reflect current interrupt mode:
Z80 instruction set consists of the following instructions:
Implied - the data value/data address is implicitly associated with the instruction.
Register - references the data in a register or in a register pair.
Register indirect - instruction specifies a register containing an address, where data is located.
Immediate - 8-bit data is provided in the instruction.
Immediate extended - 16-bit data is provided in the instruction.
Modified page zero - the destination address in zero page is calculated as N * 8, where N is a three-bit number supplied by the instruction.
Relative - one byte offset is added to the address of the next instruction. The offset is a signed number in the range -127 - +128.
Extended - the instruction operand specifies the memory address where data is located and where the program control should be transferred.
Indexed - 8-bit offset is added to the contents of an index register (IX or IY), the resulting value is a pointer to location where data resides.
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