Western Electric 32200 (WE32200) is the third and last generation of
WE32000 32-bit microprocessors. Like its predecessor
Western Electric 32100, the 32200 has
32-bit address and data buses and can address up to 4 GB physical and
virtual memory. Address and data buses on the WE32200 work not only
with 32-bit memory and peripherals, but also with 16-bit ones.
Another new feature of the 32200 is handling of non-aligned memory access.
The CPU can efficiently read and write nonaligned byte, half-word and
word data and instructions. If necessary, this feature may be disabled in
processor status word register. The WE32200 supports all 32100 instructions
and fully object code compatible with it. The processor also has
new instructions and new addressing modes, including pre- and
post-increment/decrement modes, and a few new indexed modes. The
number of registers on the WE32200 was increased from 16 to 32. Half
of these registers are general-purpose registers, and another half
are kernel registers - they are readable in any mode, but can be
changed only in kernel mode.
The 32200 CPU incorporates co-processor interface to 32206 Math
Accelerator Unit (MAU). The CPU recognizes 10 co-processor
instructions. These instructions embed actual floating-point
instruction that is executed by MAU, and they tell the
processor type and number of co-processor operands.
In addition to 32206 MAU the 32200 chipset includes 32201 Memory
Management Unit and 32204 DMA unit.
Western Electric 32200 was used in 3B2 line of AT&T comuters,
specifically in 3B2/522, 3B2/600G, 3B2/622, 3B2/700 and 3B2/1000.
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