Motorola 68010 (MC68010) microprocessor is an enhanced version of the
68000 CPU. The 68010 is based on the
same first-generation core as the 68000 and it's pin-compatible with
it. The CPU has 16-bit data bus and 24-bit address bus, i.e. it can
address up to 16 MB of memory. Programs on the 68010 can run in
supervisor or user mode. Each mode has it's own stack and status
register. The MC68010 is approximately 5% - 10% faster than the 68000
CPU at the same frequency due to few core optimizations. Some
instructions on the 68010 execute faster than on the 68000, most
notably integer multiply and divide instructions. The 68010 is faster
in processing of long word data. Also, the MC68010 microprocessor
includes special loop optimization. Whenever the CPU detects a word
instruction followed by two-word decrement and branch instruction
(DBxx), it stores the first instruction in instruction decode register
and the DBxx instruction in the prefetch queue, and then executes the
loop without fetching both instructions from memory, thus speeding up
loop processing.
In addition to slightly faster execution, the 68010 features virtual
machine and virtual memory capability:
- The 68000 CPU didn't support virtual memory because the processor
couldn't properly handle page faults (exceptions that occur when the
CPU tries to access not-mapped yet memory). When the page fault
exception was encountered, the 68000 didn't save enough information
into the stack, as a result it couldn't resume operation after the OS
handled the exception. The 68010 processes page fault exceptions
differently. When the 68010 encounters page fault it saves complete
processor status information along with other data into the stack and
transfers control to OS. After the OS loads and maps missing memory
page, the CPU restores processor status from the stack and continues
to execute the instruction that generated the exception. The next
generation of Motorola 680x0 microprocessors - Motorola 68020 and 68030 used the same "instruction
continuation" method of page fault processing.
- To fully support Virtual Machine capability one of processor
instructions - "MOVE from SR" - was made a privileged instruction. Due
to this change the 68010 was not 100% object-code compatible with the
68000. This incompatibility affected only small number of
programs, and often there was a way around it. For example, there was
a small program called DeciGEL for Amiga computers that simulated
"MOVE from SR" instruction for old applications.
- The CPU includes new supervisor register Vector Base Register (VBR).
The VBR can be used to place interrupt vector table anywhere in memory.
- New Source Function Code (SFC) and Destination Function Code (DFC)
registers specify source and destination address spaces for new MOVES
instruction. This instruction is very useful for copying data from one
memory space (user, supervisor or CPU) to other memory space.
68010 microprocessors were manufactured in plastic and ceramic DIP,
Plastic Leaded Chip Carrier and PGA packages.
|
