Motorola 68060 processor family

Motorola 68060 (MC68060) is the fourth and the last generation of 680x0 line of 32-bit microprocessors. The 68060 has two 4-stage pipelines, separate 8KB instruction and data caches, two Paged Memory Management Units - one for instructions and another for data, and two integer execution units. Like its predecessor MC68040, the 68060 integrates Floating-Point Unit compatible with Motorola 68881 / 68882 co-processors. The FPU provides hardware support only for most common floating-point instructions and data types. All unsupported instructions and data types are emulated in software.

Supervisor mode of the Motorola 68060 CPU differs from the 68040 due to changes in exception processing. User mode of the Motorola 68060 is object-compatible with MC68040, assuming that the CPU uses special software to simulate a few instructions that were present in 68040 CPU and are missing in MC68060.

The Motorola 68060 is much faster than its predecessor, mainly due to higher clock speed, superscalar design, larger instruction and data caches and branch prediction. Under the best conditions the 68060 can execute one integer instruction and one Floating-Point instruction per clock cycle, or up to 2 integer instructions and one branch instruction per clock cycle. Not all integer instructions can be executed simultaneously. Also, the CPU cannot execute the instructions out of order.

The 68060 CPU uses lower voltage - 3.3 Volt as opposed to 5 Volt for 68040. Lower core voltage directly translates into lower CPU power requirements. For example, 68060 66 MHz dissipates as much power as 68040 33 MHz. In addition to lower voltage the 68060 includes other power-saving features, such as powering down individual chip units when they are not in use, and ability to stop the clock while saving the contents of CPU registers.

Motorola also manufactured two low-cost versions of the 68060 microprocessor:

  • 68LC060 (MC68LC060) was a low-cost version without integrated FPU
  • 68EC060 (MC68EC060) was an embedded version without integrated FPU and MMU units.

Links
History
Architecture
Identification
Pinouts
Support chips
At a glance
Type:
32-bit microprocessor
Introduction:
1994
L1 cache size (KB):
8 (code) / 8 (data)
Frequency (MHz):
50 - 75

Motorola MC68EC060RC75

75 MHz
206-pin ceramic PGA
Motorola MC68EC060RC75

Motorola XC68060RC50A

50 MHz
206-pin ceramic PGA
Motorola XC68060RC50A

Motorola XC68EC060RC60E

60 MHz
206-pin ceramic PGA
Motorola XC68EC060RC60E

Motorola XC68EC060RC66E

66 MHz
206-pin ceramic PGA
Motorola XC68EC060RC66E
(c) Copyright 2003 Gennadiy Shvets