VIA Cyrix III / VIA C3

VIA Cyrix III, later renamed to C3, is a family of x86-compatible microprocessors. The first generation of Cyrix III CPUs was based on a Joshua core developed by Cyrix. This core was quickly replaced by Samuel core designed by Centaur Technology. The Samuel core was manufactured using 0.18 micro technology. The core included large 64 KB level 1 code and data caches, no level 2 cache, and had much simpler design than the Joshua core. Next core - Samuel 2 - added exclusive level 2 cache to VIA Cyrix III processors. Based on 0.15 micron technology, that core had more than 40% smaller die size, and lower core voltage and power consumption than the Samuel core. With the release of Samuel2 core the VIA Cyrix III was renamed to VIA C3. The Samuel2 core was followed by Ezra core. Manufactured on 0.13 micron technology, the Ezra core had even lower power consumption than the Samuel2 processors. A variation of Ezra core, called Ezra-T, was compatible with Tualatin bus.

The last VIA C3 core was Nehemiah. This core featured full-speed integrated FPU unit, support for SSE instructions, AES encryption and random number generator. Support for 3DNow! instructions was removed from the Nehemiah processors.

List of C3 families

VIA C3-600MHz / Cyrix III-600MHz

600 MHz (133 x 4.5, 2.0V)
370-pin ceramic PGA with heatspreader

Picture of: VIA C3-600MHz / Cyrix III-600MHz

VIA C3-750AMHz / Cyrix III-750AMHz

750 MHz (100 x 7.5, 1.6V)
370-pin ceramic PGA

Engineering Sample
Top view

Picture of: VIA C3-750AMHz / Cyrix III-750AMHz

VIA C3-933AMHz EBGA

933 MHz
133 MHz FSB
368-ball enhanced BGA

Picture of: VIA C3-933AMHz EBGA

VIA C3-1.0AGHz EBGA

1 GHz
133 MHz FSB
368-ball enhanced BGA

Picture of: VIA C3-1.0AGHz EBGA

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At a glance

Type:
32-bit microprocessor
Introduction:
2000
Technology (micron):
0.13 - 0.18
Frequency (MHz):
400 - 1400
L2 cache size (KB):
0, 64
Sockets:
BGA368
Socket 370