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Intel Celeron 466 - FV80524RX466128 (FV524RX466 128)

CPU » Celeron family » Celeron (Mendocino) » FV80524RX466128

CPU Information

General information
TypeCPU / Microprocessor
FamilyIntel Celeron
CPU part numberFV80524RX466128 (QB11ES, SL3EH)
Frequency (MHz)  ? 466
Bus speed (MHz)  ? 66
Clock multiplier  ? 7
Package370-pin Plastic Staggered Pin Grid Array
1.95" x 1.95" (4.95 cm x 4.95 cm)
SocketSocket 370 (PGA370)
Introduction date26-Apr-99
Price at introduction$169
 
Architecture / Microarchitecture
Processor coreMendocino
Core steppingB0 (SL3EH)
Manufacturing process0.25 micron
19 million transistors
Data width32 bit
Floating Point UnitIntegrated
Level 1 cache size  ? 16 KB code
16 KB data
Level 2 cache size  ? 128 KB
Physical memory (GB)4
FeaturesMMX technology
Low power features
  • AutoHALT state  ? 
  • Stop Grant state  ? 
  • Sleep state  ? 
  • Deep Sleep state  ? 
 
Electrical/Thermal parameters
V core (V)  ? 2
Minimum/Maximum operating temperature (°C)  ? 5 - 70
Maximum power dissipation (W)  ? 25.7

Pictures (8)

Bottom view

466 MHz
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)

Bottom view		 Intel Celeron 466 - FV80524RX466128 (FV524RX466 128)
Top view

466 MHz
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)

Top view		 Intel Celeron 466 - FV80524RX466128 (FV524RX466 128)
Engineering sample - bottom view

466 MHz
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)

Engineering sample
Bottom view		 Intel Celeron 466 - FV80524RX466128 (FV524RX466 128)
Engineering sample - top view

466 MHz
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)

Engineering sample
Top view		 Intel Celeron 466 - FV80524RX466128 (FV524RX466 128)
Engineering sample in OEM box - back view

466 MHz
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)

Engineering sample
OEM boxed version
Bottom view		 Intel Celeron 466 - FV80524RX466128 (FV524RX466 128)
Engineering sample in OEM box - front view

466 MHz
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)

Engineering sample
OEM boxed version
Top view		 Intel Celeron 466 - FV80524RX466128 (FV524RX466 128)
 
2008-06-20 16:07:11
Posted by: sampppa

  		 
picture
2008-01-06 18:59:30
Posted by: menon maurizio

  		picture
Add picture

Benchmarks

Tested processor
CPU ID:0665h
CPU vendor string:GenuineIntel
 
Motherboard Epox EP-693A (MS-DOS)
Dhrystone 2.1 (VAX MIPS)463.6
Doom 1.9s high detail (FPS)91.01
Doom 1.9s low detail (FPS)144.47
Linpack 100x100 (MFLOPS)168.86
Whetstone (KWIPS)249.35
 
Motherboard Epox EP-693A (Win98)
Sandra Dhrystone (MIPS)1598
Sandra MultiMedia Floating Point (it/s)1162
Sandra MultiMedia Integer (it/s)3080
Sandra Whetstone (MFLOPS)621
 
Tested processor
CPU ID:0665h
CPU vendor string:GenuineIntel
 
Motherboard Epox EP-693A (MS-DOS)
Dhrystone 2.1 (VAX MIPS)463.6
Doom 1.9s high detail (FPS)91.05
Doom 1.9s low detail (FPS)144.19
Linpack 100x100 (MFLOPS)168.91
Whetstone (KWIPS)249.35
 
Motherboard Epox EP-693A (Win98)
Sandra Dhrystone (MIPS)1593
Sandra MultiMedia Floating Point (it/s)1158
Sandra MultiMedia Integer (it/s)3070
Sandra Whetstone (MFLOPS)619

CPU ID

NOTE: CPU ID information below was taken from one CPU and may include features that are not present in all different steppings of the Intel Celeron 466 CPU.

Manufacturer:Intel
Family:Celeron
Model / Processor Number:466
Part number:FV80524RX466128
S-Spec / Comment:SL3EH
Submitted by:Neon
General information
Vendor:GenuineIntel
Processor type:Original OEM Processor
CPUID signature:665
Family: 6 (06h)
Model: 6 (06h)
Stepping: 5 (05h)
TLB/Cache details:Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Data TLB: 4-MB Pages, 4-way set associative, 8 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 32 entries
Instruction TLB: 4-MB Pages, fully associative, 2 entries

Cache: L1 (data) L1 (instruction) L2
Size: 16 KB 16 KB 128 KB
Associativity: 4-way set associative 4-way set associative 4-way set associative
Line size: 32 bytes 32 bytes 32 bytes
 
Instruction set extensionsAdditonal instructions
MMX CMOV
  CMPXCHG8B
  FXSAVE/FXRSTORE
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
  Debugging extensions
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Physical address extensions
  Time stamp counter
  Virtual 8086-mode enhancements

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Last modified: 30 Oct 2009
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