Intel Celeron 500 MHz - FV80524RX500128 (FV524RX500 128)
Specifications
| General information | ||||||||||
| Type | CPU / Microprocessor | |||||||||
| Market segment | Desktop | |||||||||
| Family | Intel Celeron | |||||||||
| CPU part number | FV80524RX500128 is an OEM/tray microprocessor | |||||||||
| Frequency ? | 500 MHz | |||||||||
| Bus speed ? | 66 MHz | |||||||||
| Clock multiplier ? | 7.5 | |||||||||
| Package | 370-pin Plastic Staggered Pin Grid Array 1.95" x 1.95" (4.95 cm x 4.95 cm) | |||||||||
| Socket | Socket 370 (PGA370) | |||||||||
| S-spec numbers | ||||||||||
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| Architecture / Microarchitecture | ||||||||||
| Microarchitecture | P6 | |||||||||
| Processor core ? | Mendocino | |||||||||
| Core stepping ? | B0 (SL3FY) | |||||||||
| CPUID | 665 (SL3FY) | |||||||||
| Manufacturing process | 0.25 micron 19 million transistors | |||||||||
| Data width | 32 bit | |||||||||
| Floating Point Unit | Integrated | |||||||||
| Level 1 cache size ? | 16 KB code 16 KB data | |||||||||
| Level 2 cache size ? | 128 KB | |||||||||
| Physical memory | 4 GB | |||||||||
| Features | MMX technology | |||||||||
| Low power features |
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| Electrical/Thermal parameters | ||||||||||
| V core ? | 2V | |||||||||
| Minimum/Maximum operating temperature ? | 5°C - 70°C | |||||||||
| Maximum power dissipation ? | 27.2 Watt | |||||||||
CPUs, related to Intel Celeron 500 MHz (FV80524RX500128)
• Highlighted numbers and features indicate whether specific processor performs better or worse than Celeron 500 MHz (FV80524RX500128)
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• List of related CPUs is not complete.
• Features abbreviations:
SSE - SSE instructions
Pictures (4)
| Bottom view | |
500 MHz 128 KB L2 cache Plastic Pin Grid Array package (socket 370) Bottom view |
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| Top view | |
500 MHz 128 KB L2 cache Plastic Pin Grid Array package (socket 370) Top view |
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| Engineering sample - bottom view | |
500 MHz 128 KB L2 cache Plastic Pin Grid Array package (socket 370) Engineering sample Bottom view |
.jpg) |
| Engineering sample - top view | |
500 MHz 128 KB L2 cache Plastic Pin Grid Array package (socket 370) Engineering sample Top view |
.jpg) |
Benchmarks
| Tested processor | ||||||||||||||||||||||||||||||||||||||||
| CPU ID: | 0665h | |||||||||||||||||||||||||||||||||||||||
| CPU vendor string: | GenuineIntel | |||||||||||||||||||||||||||||||||||||||
Integer performance
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Floating Point performance
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MMX / SSE / SSE2 performance
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| Tested processor | ||||||||||||||||||||||||||||||||||||||||
| CPU ID: | 0665h | |||||||||||||||||||||||||||||||||||||||
| CPU vendor string: | GenuineIntel | |||||||||||||||||||||||||||||||||||||||
Integer performance
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Floating Point performance
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MMX / SSE / SSE2 performance
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CPU ID (1)
NOTE: CPU ID information below was taken from one CPU and may include features that are not present in all different steppings of the Intel Celeron 500 CPU.
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| General information | |
|---|---|
| Vendor: | GenuineIntel |
| Processor type: | Original OEM Processor |
| CPUID signature: | 665 |
| Family: | 6 (06h) |
| Model: | 6 (06h) |
| Stepping: | 5 (05h) |
| TLB/Cache details: | Data TLB: 4-KB Pages, 4-way set associative, 64 entries Data TLB: 4-MB Pages, 4-way set associative, 8 entries Instruction TLB: 4-KB Pages, 4-way set associative, 32 entries Instruction TLB: 4-MB Pages, fully associative, 2 entries |
| Cache: | L1 data | L1 instruction | L2 |
|---|---|---|---|
| Size: | 16 KB | 16 KB | 128 KB |
| Associativity: | 4-way set associative |
4-way set associative |
4-way set associative |
| Line size: | 32 bytes | 32 bytes | 32 bytes |
| Instruction set extensions | Additional instructions | ||
|---|---|---|---|
| MMX | CMOV | ||
| CMPXCHG8B | |||
| FXSAVE/FXRSTORE | |||
| SYSENTER/SYSEXIT | |||
| Major features | Other features | ||
| On-chip Floating Point Unit | 36-bit page-size extensions | ||
| Debugging extensions | |||
| Machine check architecture | |||
| Machine check exception | |||
| Memory-type range registers | |||
| Model-specific registers | |||
| Page attribute table | |||
| Page global extension | |||
| Page-size extensions (4MB pages) | |||
| Physical address extensions | |||
| Time stamp counter | |||
| Virtual 8086-mode enhancements | |||
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Process size
The process size for these should be 250 nm.
I hate using Wikipedia to validate things, but under "List_of_Intel_Celeron_microprocessors", all Mendocino cores are reported as 250 nm.
Additionally, the SL3FY link on the page also confirms the 250 nm process size.