CPU ID
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Mobile Intel Celeron 1.50 GHz CPU.
| Manufacturer: | Intel |
| Family: | Mobile Intel Celeron |
| Model / Processor Number: | 1.50 GHz |
|
| Part number: | RH80532NC021256 |
| S-Spec / Comment: | SL6FN |
| Submitted by: | cocoe |
|
| General information |
|---|
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Mobile Intel(R) Celeron(R) CPU 1.50GHz |
| Logical processors: | 1 |
| Processor type: | Original OEM Processor |
| CPUID signature: | F24 |
| Family: | 15 (0Fh) |
| Model: | 2 (02h) |
| Stepping: | 4 (04h) |
| TLB/Cache details: | Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries
Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 entries
No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache |
| Cache: |
L1 (data) |
L1 (instruction) |
L2 |
|---|
| Size: |
8 KB |
12K uops |
256 KB |
| Associativity: |
4-way set associative |
8-way set associative |
4-way set associative |
| Line size: |
64 bytes |
|
64 bytes |
| Other: |
sectored cache |
|
sectored cache |
| |
| Instruction set extensions | Additonal instructions |
|---|
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG8B |
| |
FXSAVE/FXRSTORE |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
|---|
| On-chip Floating Point Unit |
36-bit page-size extensions |
| |
Debug store |
| |
Debugging extensions |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Model-specific registers |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Physical address extensions |
| |
Self-snoop |
| |
Thermal monitor |
| |
Thermal monitor and software controlled clock facilities |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
