Intel Celeron (Mendocino) microprocessor family
| Previous Generation | Related Family | Next Generation | |
|---|---|---|---|
Celeron (Covington)
Slot 1 |
Celeron (Mendocino)
Slot 1 Socket 370 |
Mobile Celeron (Mendocino)
|
Celeron (Coppermine)
Socket 370 |
Celeron processors based on Mendocino core were released in 1998 in SEPP (Slot1)
and plastic PGA (Socket 370) packages, but already in 1999 the SEPP package
was phased out by Intel in favor of PPGA package. Plastic PGA (socket 370)
CPUs were cheaper to manufacture, and moving to new proprietary socket
allowed Intel to further separate high-end and budget processor markets.
All Celeron processors with Mendocino core were manufactured using 0.25 micron
technology and had 128 KB on-chip L2 cache running at full processor speed.
The processors in PPGA package were produced at speeds ranging from 300 to 533 MHz,
and processors in SEPP package were produced at speeds 300 - 433 MHz.
Production parts
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300 MHz
128 KB L2 cache
Single Edge Processor package (slot 1)
Front view
Image reduced 2x times
The first microprocessor based on Mendocino core. This processor is marked as "300A/66", the suffix "A" is used to distinguish it from older Covington Celeron 300/66 CPU. New feature in this Celeron was integrated 128 KB L2 cache running at the processor speed. Addition of the L2 cache was the main reason why the performance of this CPU was much better than performance of older Covington Celerons. Like the older Celeron 266, the Celeron 300A was a very good overclocker. It was possible to run the CPU at 450 MHz by using 100 MHz bus speed.
128 KB L2 cache
Single Edge Processor package (slot 1)
Front view
Image reduced 2x times
The first microprocessor based on Mendocino core. This processor is marked as "300A/66", the suffix "A" is used to distinguish it from older Covington Celeron 300/66 CPU. New feature in this Celeron was integrated 128 KB L2 cache running at the processor speed. Addition of the L2 cache was the main reason why the performance of this CPU was much better than performance of older Covington Celerons. Like the older Celeron 266, the Celeron 300A was a very good overclocker. It was possible to run the CPU at 450 MHz by using 100 MHz bus speed.
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333 MHz
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Bottom view
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Bottom view
.jpg)
333 MHz
128 KB L2 cache
Single Edge Processor package (slot 1)
Mendocino core
Front view
Image reduced 2x times
128 KB L2 cache
Single Edge Processor package (slot 1)
Mendocino core
Front view
Image reduced 2x times
.jpg)
366 MHz
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Bottom view
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Bottom view
.jpg)
366 MHz
128 KB L2 cache
Single Edge Processor package (slot 1)
Mendocino core
Engineering sample
Front view
Image reduced 2x times
128 KB L2 cache
Single Edge Processor package (slot 1)
Mendocino core
Engineering sample
Front view
Image reduced 2x times
.jpg)
400 MHz
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Boxed version of the processor
Bottom view
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Boxed version of the processor
Bottom view
.jpg)
400 MHz
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Bottom view
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Bottom view
.jpg)
400 MHz
128 KB L2 cache
Single Edge Processor package (slot 1)
Mendocino core
Engineering sample
Front view
Image reduced 2x times
128 KB L2 cache
Single Edge Processor package (slot 1)
Mendocino core
Engineering sample
Front view
Image reduced 2x times
.jpg)
433 MHz
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Boxed version of the processor
Bottom view
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Boxed version of the processor
Bottom view
.jpg)
433 MHz
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Engineering sample
Bottom view
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Engineering sample
Bottom view
.jpg)
433 MHz
128 KB L2 cache
Single Edge Processor package (slot 1)
Mendocino core
Engineering sample
Front view
Image reduced 2x times
128 KB L2 cache
Single Edge Processor package (slot 1)
Mendocino core
Engineering sample
Front view
Image reduced 2x times
.jpg)
466 MHz
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Bottom view
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Bottom view
.jpg)
500 MHz
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Bottom view
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Bottom view
.jpg)
533 MHz
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Bottom view
128 KB L2 cache
Plastic Pin Grid Array package (socket 370)
Bottom view
Samples only
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At a glance
Type:
32-bit microprocessor
Technology (micron):
0.25
Frequency (MHz):
300 - 533
L2 cache size (KB):
128
Sockets:
Slot 1
Socket 370
Socket 370
Celeron (Mendocino) 466