Intel Celeron D 310 - RK80546RE046256 / NE80546RE046256 (BX80546RE2130C)

CPU Information

General information
TypeCPU / Microprocessor
FamilyIntel Celeron D (Prescott)
Model number  ? 310
CPU part numbersRK80546RE046256 (SL8RZ)
NE80546RE046256 (SL8S2)
B80546RE046256 (SL8S4, SL93R)
Box part numberBX80546RE2130C (SL8RZ, SL8S2, SL93R)
Frequency (MHz)  ? 2133
Bus speed (MHz)  ? 533
Clock multiplier  ? 16
Package478-pin Flip-Chip Pin Grid Array (FC-PGA2) package
1.38" x 1.38" (3.5 cm x 3.5 cm)
SocketSocket 478 (mPGA478b)
 
Architecture / Microarchitecture
Processor corePrescott-256
Core steppingsE0 (SL8RZ)
G0 (SL8S4)
G1 (SL8S2, SL93R)
Manufacturing process0.09 micron
Data width32 bit
Floating Point UnitIntegrated
Level 1 cache size  ? 16 KB data cache
Level 2 cache size  ? 256 KB 4-way set associative cache
Features
  • MMX technology
  • SSE
  • SSE2
  • SSE3
Low power features
  • AutoHALT state  ? 
  • Stop Grant state  ? 
  • Sleep state  ? 
 
Electrical/Thermal parameters
V core (V)  ? 1.25 - 1.4
Minimum/Maximum operating temperature (°C)  ? 5 - 67
Thermal Design Power (W)  ? 73
 
Notes on Intel RK80546RE046256
  • Bus frequency is 133 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 533 MHz
  • The part NE80546RE046256 is RoHS compliant

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CPU ID

NOTE: CPU ID information below was taken from one CPU and may include features that are not present in all different steppings of the Intel Celeron D 2.13 GHz CPU.

Manufacturer:Intel
Family:Celeron D
Model / Processor Number:2.13 GHz
Part number:RK80546RE046256
S-Spec / Comment:SL8S2
Submitted by:cocoe
General information
Vendor:GenuineIntel
Processor name (BIOS): Intel(R) Celeron(R) CPU 2.13GHz
Cores:1
Logical processors:1
Processor type:Original OEM Processor
CPUID signature:F49
Family:15 (0Fh)
Model: 4 (04h)
Stepping: 9 (09h)
TLB/Cache details:Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries
Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries
No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache

Cache: L1 (data) L1 (instruction) L2
Size: 16 KB 12K uops 256 KB
Associativity: 8-way set associative 8-way set associative 4-way set associative
Line size: 64 bytes   64 bytes
Other: sectored cache   sectored cache
 
Instruction set extensionsAdditonal instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG8B
SSE3 FXSAVE/FXRSTORE
  MONITOR/MWAIT
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
  64-bit debug store
  Advanced programmable interrupt controller
  CPL qualified debug store
  Debug store
  Debugging extensions
  L1 context ID
  LAHF/SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Physical address extensions
  Self-snoop
  Thermal monitor
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control

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