CPU Information
Celeron Dual-Core E1200 is a dual-core version of
Celeron 420. Both processors are based on a Core micro-architecture, have the same core and front-side bus frequency, and the same size of L1 and L2 caches. Having one extra core, the E1200 outperforms the Celeron 420 in multi-threaded applications (in some well-designed applications by almost 100%), and, thanks to L2 cache shared between two cores, the E1200 can perform as fast as the Celeron 420 in single-threaded applications.
Having only 512 KB of level 2 cache, the Celeron E1200 processor performs 5% - 10% slower in business applications than the
Pentium Dual-Core E2140, or up to 15% slower in games and other memory-intensive applications.
| General information |
| Type | CPU / Microprocessor |
| Family | Intel Celeron Dual-Core |
| Model number ? | E1200 |
| CPU part number | HH80557PG025D (SLAQW) |
| Box part numbers | BX80557E1200 (SLAQW)
BXC80557E1200F (SLAQW) |
| Frequency (MHz) ? | 1600 |
| Bus speed (MHz) ? | 800 |
| Clock multiplier ? | 8 |
| Package | 775-land Flip Chip LGA (FC-LGA6)
1.48" x 1.48" (3.75 cm x 3.75 cm) |
| Socket | Socket 775 (LGA775) |
| Introduction date | Jan 22, 2008 |
| Price at introduction | $53 |
| |
| Architecture / Microarchitecture |
| Processor core | Allendale |
| Core stepping | M0 (SLAQW) |
| Manufacturing process | 0.065 micron |
| Data width | 64 bit |
| Number of cores | 2 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 2 x 32 KB instruction caches
2 x 32 KB data caches |
| Level 2 cache size ? | 512 KB 8-way set associative shared cache |
| Features | - MMX technology
- SSE
- SSE2
- SSE3
- Execute Disable bit ?
- EM64T technology ?
|
| Low power features | - HALT state
- Extended HALT state
- Stop Grant state ?
- Extended Stop Grant state
- Enhanced SpeedStep technology ?
|
| |
| Electrical/Thermal parameters |
| V core (V) ? | 0.85 - 1.5 |
| Minimum/Maximum operating temperature (°C) ? | 5 - 73.3 |
| Minimum/Maximum power dissipation (W) ? | 8 (TDP for Extended HALT mode) / 111.15 |
| Thermal Design Power (W) ? | 65 |
| |
| Notes on Intel HH80557PG025D |
- Bus frequency is 200 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 800 MHz
- BXC80557E1200F is a Chinese version
|
CPU ID
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Celeron Dual-Core E1200 CPU.
| Manufacturer: | Intel |
| Family: | Celeron Dual-Core |
| Processor Number: | E1200 |
|
| Part number: | HH80557PG025D |
| S-Spec / Comment: | SLAQW |
| Submitted by: | CPU-World |
|
| General information |
|---|
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Celeron(R) CPU E1200 @ 1.60GHz |
| Cores: | 2 |
| Logical processors: | 2 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 6FD |
| Family: | 6 (06h) |
| Model: | 15 (0Fh) |
| Stepping: | 13 (0Dh) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
|---|
| Size: |
32 KB |
32 KB |
512 KB |
| Associativity: |
8-way set
associative |
8-way set
associative |
2-way set
associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
| |
| Instruction set extensions | Additonal instructions |
|---|
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| |
MONITOR/MWAIT |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
|---|
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| Enhanced SpeedStep |
CPL qualified debug store |
| |
Debug store |
| |
Debugging extensions |
| |
LAHF/SAHF support in 64-bit mode |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Model-specific registers |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Pending break enable |
| |
Perfmon and Debug capability |
| |
Physical address extensions |
| |
Self-snoop |
| |
Thermal monitor |
| |
Thermal monitor and software controlled clock facilities |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
| |
xTPR Update Control |
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