CPU Information
| General information |
| Type | CPU / Microprocessor |
| Family | Intel Celeron M |
| Model number ? | 530 |
| CPU part number | LF80537NE0301M (QVGX, QVTG, QVTH, QWLO, SL9UY, SL9VA, SLGFL) |
| Box part numbers | BX80537NE0301M (SL9VA)
BX80537530 (SL9VA) |
| Frequency (MHz) ? | 1733 |
| Bus speed (MHz) ? | 533 |
| Clock multiplier ? | 13 |
| Package | 478-pin micro FC-PGA
1.38" x 1.38" (3.5 cm x 3.5 cm) |
| Socket | Socket M |
| Weight | 0.2oz / 5.6g |
| Introduction date | Sep 5, 2007 |
| Price at introduction | $86 |
| | | Architecture / Microarchitecture |
| Processor core | Merom |
| Core steppings | A1 (QVGX, QVTG, QVTH)
B2 (SL9UY, SL9VA)
E1 (QWLO)
G0 (SLGFL) |
| Manufacturing process | 0.065 micron process with copper interconnect |
| Data width | 64 bit |
| Number of cores | 1 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 32 KB instruction cache
32 KB write-back data cache |
| Level 2 cache size ? | 1 MB |
| Features | - MMX technology
- SSE
- SSE2
- SSE3
- Supplemental SSE3
- Execute disable bit ?
- EM64T technology ?
|
| Low power features | - Core C1/AutoHalt, C1/MWAIT, C2 and C3 modes
- Stop Grant mode ?
- Sleep mode ?
- Deep Sleep mode ?
- FSB low-power enhancements
|
| | | Electrical/Thermal parameters |
| V core (V) ? | 0.95 - 1.3 |
| Minimum/Maximum operating temperature (°C) ? | 0 - 100 |
| Minimum/Maximum power dissipation (W) ? | 26.41 (Deep Sleep mode) / 45.31 |
| Thermal Design Power (W) ? | 26 (CPU ID 06F6h)
30 |
| |
| Notes on Intel LF80537NE0301M |
- Bus frequency is 133 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 533 MHz
- This part is also offered as an embedded microprocessor
- Celeron M 530 microprocessors were offered in socket M-compatible and socket P-compatible packages. Please verify compatibility with your system before buying the processor
|
Benchmarks
| Tested processor |
| S-spec number: | SL9VA |
| CPU ID: | 0661h |
| CPU vendor string: | GenuineIntel |
| CPU name string: | Intel(R) Celeron(R) M CPU 530 @ 1.73GHz |
| |
| Motherboard AOpen i975Xa-YDG |
| 3DMark03 CPU score | 713 |
| 3DMark03 game score | 2963 |
| 3DMark2001 score | 9907 |
| 7Zip compressing/decompressing speed | 1426 |
| CINEBENCH R10 CPU score | 1597 |
| CINEBENCH R10 CPU score (1 core) | 1597 |
| CINEBENCH R10 OpenGL score | 1925 |
| CINEBENCH R10 render time (seconds) | 553.8 |
| Dhrystone 2.1 (VAX MIPS) | 2874.1 |
| Doom 1.9s high detail (FPS) | 139.18 |
| Doom 1.9s low detail (FPS) | 225.65 |
| Euler3D | 0.39 |
| Linpack 100x100 (MFLOPS) | 1085.64 |
| PCMark2002 CPU score | 6755 |
| PCMark2002 Memory score | 7354 |
| Sandra Dhrystone (MIPS) | 10419 |
| Sandra MultiMedia Floating Point (it/s) | 25650 |
| Sandra MultiMedia Integer (it/s) | 22882.7 |
| Sandra Whetstone (MFLOPS) | 2625 |
| Sandra Whetstone SSE2 (MFLOPS) | 3872.33 |
| Super PI (1M) | 39.77 |
| Whetstone (KWIPS) | 1169.89 |
| WinRAR compressing/decompressing speed | 336.33 |
| wPrime v1.55 (32M) | 105.02 |
CPU ID
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Celeron M 530 CPU.
| Manufacturer: | Intel |
| Family: | Celeron M |
| Model / Processor Number: | 530 |
|
| Part number: | LF80537NE0301M |
| S-Spec / Comment: | SL9VA |
| Submitted by: | CPU-World |
|
| General information |
|---|
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Celeron(R) M CPU 530 @ 1.73GHz |
| Cores: | 1 |
| Logical processors: | 1 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 10661 |
| Family: | 6 (06h) |
| Model: | 22 (016h) |
| Stepping: | 1 (01h) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: |
L1 (data) |
L1 (instruction) |
L2 |
|---|
| Size: |
32 KB |
32 KB |
1 MB |
| Associativity: |
8-way set associative |
8-way set associative |
4-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
| |
| Instruction set extensions | Additonal instructions |
|---|
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| |
MONITOR/MWAIT |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
|---|
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| |
CPL qualified debug store |
| |
Debug store |
| |
Debugging extensions |
| |
LAHF/SAHF support in 64-bit mode |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Model-specific registers |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Pending break enable |
| |
Perfmon and Debug capability |
| |
Physical address extensions |
| |
Self-snoop |
| |
Thermal monitor |
| |
Thermal monitor and software controlled clock facilities |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
| |
xTPR Update Control |
|
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