Intel Celeron M microprocessor family
Intel Celeron M, low-cost version of mobile microprocessors, was introduced in January of 2004. Based on the same micro-architecture as Pentium M, the Celeron processors included all performance enhancements that were incorporated into Pentium M CPUs: separate 32 KB level 1 data and instruction caches, L2 cache with advanced transfer architecture, 400 Mhz Front Side Bus, branch prediction, data prefetch logic, and support for MMX, SSE and SSE2 instructions. Support for SSE3 was added in more recent versions of Celeron M. The size of level 2 cache in Celeron M CPUs was slashed in half - from 1 MB to 512 KB for processors with Banias core, and from 2 MB to 1 MB for processors with Dothan core. The Celeron M microprocessors included many, but not all of power-saving features that were present in Pentium M processors. Celeron M CPUs didn't support Deeper Sleep mode - this mode provided the lowest power consumption for Pentium M processors. Enhanced SpeedStep technology, which reduces CPU's core voltage and frequency at times when maximum processor performance is not required, was not included too. Some, but not all, Celeron M processors support Execute Disable bit functionality. Celeron M 5xx series processors include Supplemental SSE3 instructions and support 64-bit mode.
The Celeron M processors were manufactured in 479-ball micro FC-BGA package and 478-pin micro FC-PGA, and could work in the same motherboards as Pentium M processors.
At a glance
32, 64-bit microprocessor
Jan 5, 2004
0.045 - 0.13
0.6 - 2.26
L2 cache size (MB):