Intel Core 2 Duo Mobile T5300 LF80537GE0302M
Specifications
| General information | ||||||||||
| Type | CPU / Microprocessor | |||||||||
| Market segment | Mobile | |||||||||
| Family | Intel Core 2 Duo Mobile | |||||||||
| Model number ? | T5300 | |||||||||
| CPU part number | LF80537GE0302M is an OEM/tray microprocessor | |||||||||
| Frequency ? | 1733 MHz | |||||||||
| Bus speed ? | 533 MHz | |||||||||
| Clock multiplier ? | 13 | |||||||||
| Package | 478-pin micro-FCPGA 1.38" x 1.38" (3.5 cm x 3.5 cm) | |||||||||
| Socket | Socket M | |||||||||
| S-spec numbers | ||||||||||
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| Architecture / Microarchitecture | ||||||||||
| Microarchitecture | Core | |||||||||
| Platform | Napa Refresh | |||||||||
| Processor core ? | Merom | |||||||||
| Core stepping ? | L2 (QUFY, SL9WE) | |||||||||
| CPUID | 6F2 (QUFY, SL9WE) | |||||||||
| Manufacturing process | 0.065 micron | |||||||||
| Data width | 64 bit | |||||||||
| The number of cores | 2 | |||||||||
| The number of threads | 2 | |||||||||
| Floating Point Unit | Integrated | |||||||||
| Level 1 cache size ? | 2 x 32 KB instruction caches 2 x 32 KB write-back data caches | |||||||||
| Level 2 cache size ? | shared 2 MB | |||||||||
| Features |
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| Low power features |
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| Electrical/Thermal parameters | ||||||||||
| Minimum/Maximum operating temperature ? | 0°C - 100°C | |||||||||
| Thermal Design Power ? | 34 Watt | |||||||||
| Notes on Intel LF80537GE0302M | ||||||||||
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CPUs, related to Intel Core 2 Duo T5300
| Model | Cores / Threads |
Freq. | L2 cache |
TDP | Features |
|---|---|---|---|---|---|
| Intel Core 2 Duo Mobile family, Socket M | |||||
| Intel Core 2 Duo T5200 | 2 / 2 | 1.6 GHz | 2 MB | 34 Watt | ESS |
| Intel Core 2 Duo T5500 (Socket M) | 2 / 2 | 1.66 GHz | 2 MB | 34 Watt | ESS |
| Intel Core 2 Duo T5600 (Socket M) | 2 / 2 | 1.83 GHz | 2 MB | 34 Watt | VT, ESS |
| Intel Core 2 Duo T7200 (Socket M) | 2 / 2 | 2 GHz | 4 MB | 34 Watt | VT, ESS |
| Intel Core 2 Duo T7400 (Socket M) | 2 / 2 | 2.16 GHz | 4 MB | 34 Watt | VT, ESS |
| Intel Core 2 Duo T7600 (Socket M) | 2 / 2 | 2.33 GHz | 4 MB | 34 Watt | VT, ESS |
| Intel Core 2 Duo T7600G | 2 / 2 | 2.33 GHz | 4 MB | VT, ESS, Unlock | |
| Intel Core 2 Duo Mobile family, Core micro-architecture, Other sockets | |||||
| Intel Core 2 Duo P9700 | 2 / 2 | 2.8 GHz | 6 MB | 28 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo T9600 (BGA) | 2 / 2 | 2.8 GHz | 6 MB | 35 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo T9600 (Socket P) | 2 / 2 | 2.8 GHz | 6 MB | 35 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo E8335 | 2 / 2 | 2.93 GHz | 6 MB | SSE4, ESS | |
| Intel Core 2 Duo T9800 | 2 / 2 | 2.93 GHz | 6 MB | 35 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo E8435 | 2 / 2 | 3.06 GHz | 6 MB | SSE4, ESS | |
| Intel Core 2 Duo T9900 (Socket P) | 2 / 2 | 3.06 GHz | 6 MB | 35 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo T9900 (BGA) | 2 / 2 | 3.06 GHz | 6 MB | 35 Watt | SSE4, VT, TXT, ESS, TBT |
| Other families, Core micro-architecture, Socket M | |||||
| Intel Celeron M 520 | 1 / 1 | 1.6 GHz | 1 MB | 30 Watt | ESS |
| Intel Celeron M 530 (Socket M) | 1 / 1 | 1.73 GHz | 1 MB | 30 Watt | ESS |
• Highlighted numbers and features indicate whether specific processor performs better or worse than Core 2 Duo T5300
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• List of related CPUs is not complete.
• Features abbreviations:
SSE4 - SSE4 instructions
VT - Virtualization
TXT - Trusted Execution
ESS - PowerNow! / Enhanced SpeedStep
TBT - Dynamic Acceleration / Turbo Boost
Unlock - Unlocked multiplier
VT - Virtualization
TXT - Trusted Execution
ESS - PowerNow! / Enhanced SpeedStep
TBT - Dynamic Acceleration / Turbo Boost
Unlock - Unlocked multiplier
Pictures (1)
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CPU ID (1)
NOTE: CPU ID information below was taken from one CPU and may include features that are not present in all different steppings of the Intel Core 2 Duo Mobile T5300 CPU.
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| General information | |
|---|---|
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Core(TM)2 CPU T5300 @ 1.73GHz |
| Cores: | 2 |
| Logical processors: | 2 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 6F2 |
| Family: | 6 (06h) |
| Model: | 15 (0Fh) |
| Stepping: | 2 (02h) |
| TLB/Cache details: | 64-byte Prefetching Data TLB: 4-KB Pages, 4-way set associative, 256 entries Data TLB: 4-MB Pages, 4-way set associative, 32 entries Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: | L1 data | L1 instruction | L2 |
|---|---|---|---|
| Size: | 2 x 32 KB | 2 x 32 KB | 2 MB |
| Associativity: | 8-way set associative |
8-way set associative |
8-way set associative |
| Line size: | 64 bytes | 64 bytes | 64 bytes |
| Comments: | Shared between all cores |
| Instruction set extensions | Additional instructions | ||
|---|---|---|---|
| MMX | CLFLUSH | ||
| SSE | CMOV | ||
| SSE2 | CMPXCHG16B | ||
| SSE3 | CMPXCHG8B | ||
| SSSE3 | FXSAVE/FXRSTORE | ||
| MONITOR/MWAIT | |||
| SYSENTER/SYSEXIT | |||
| Major features | Other features | ||
| On-chip Floating Point Unit | 36-bit page-size extensions | ||
| 64-bit / Intel 64 | 64-bit debug store | ||
| Enhanced SpeedStep | Advanced programmable interrupt controller | ||
| CPL qualified debug store | |||
| Debug store | |||
| Debugging extensions | |||
| Digital Thermal Sensor capability | |||
| LAHF/SAHF support in 64-bit mode | |||
| Machine check architecture | |||
| Machine check exception | |||
| Memory-type range registers | |||
| Model-specific registers | |||
| Page attribute table | |||
| Page global extension | |||
| Page-size extensions (4MB pages) | |||
| Pending break enable | |||
| Perfmon and Debug capability | |||
| Physical address extensions | |||
| Self-snoop | |||
| Thermal monitor | |||
| Thermal monitor 2 | |||
| Thermal monitor and software controlled clock facilities | |||
| Time stamp counter | |||
| Virtual 8086-mode enhancements | |||
| xTPR Update Control | |||
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