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Intel Core 2 Duo Mobile T8300 FF80577GG0563M (BX80577T8300)
Specifications
| General information |
| Type | CPU / Microprocessor |
| Market segment | Mobile |
| Family | Intel Core 2 Duo Mobile |
| Model number ? | T8300 |
| CPU part numbers | FF80577GG0563M is an OEM/tray microprocessor BX80577T8300 is a boxed microprocessor |
| Frequency (MHz) ? | 2400 |
| Bus speed (MHz) ? | 800 |
| Clock multiplier ? | 12 |
| Package | 478-pin micro-FCPGA
1.38" x 1.38" (3.5 cm x 3.5 cm) |
| Socket | Socket P |
| Introduction date | Jan 7, 2008 |
| Price at introduction | $241 |
| | | S-spec numbers |
| |
ES/QS processors |
Production processors |
| Part number |
Q5CP |
Q8LG |
SLAPA |
SLAYQ |
| BX80577T8300 | | | + | + |
| FF80577GG0563M | + | + | + | + |
|
| | | Architecture / Microarchitecture |
| Microarchitecture | Core |
| Platform | Santa Rosa
Santa Rosa Refresh |
| Processor core ? | Penryn-3M |
| Core steppings ? | B1 (Q5CP) M0 (SLAPA, SLAYQ) |
| CPUIDs | 674 (Q5CP) 10676 (SLAPA, SLAYQ) |
| Manufacturing process | 0.045 micron |
| Data width | 64 bit |
| The number of cores | 2 |
| The number of threads | 2 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 2 x 32 KB instruction caches
2 x 32 KB write-back data caches |
| Level 2 cache size ? | shared 3 MB |
| Features | - MMX instruction set
- SSE
- SSE2
- SSE3
- Supplemental SSE3
- SSE4.1 ?
- EM64T technology ?
- Execute Disable Bit technology ?
- Virtualization Technology ?
- Dynamic Acceleration technology ?
|
| Low power features | - C1/AutoHALT, C1/MWAIT, C2, C3, C4 and C6 core states
- Stop Grant mode ?
- Sleep mode ?
- Deep Sleep mode ?
- Deeper Sleep mode ?
- Enhanced Deeper Sleep mode ?
- Deep Power-Down state ?
- Dynamic FSB Frequency switching ?
- Enhanced SpeedStep technology ?
|
| | | Electrical/Thermal parameters |
| V core (V) ? | 1 - 1.25 |
| Minimum/Maximum operating temperature (°C) ? | 0 - 105 |
| Minimum/Maximum power dissipation (W) ? | 3.92 (Deep Power-Down mode) / 53.89 |
| Thermal Design Power (W) ? | 35 |
| |
| Notes on Intel FF80577GG0563M |
- Bus frequency is 200 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 800 MHz
- Processor operates at 0.85 Volt - 1.025 Volt in Low Frequency mode
- Processor operates at 0.75 Volt - 0.95 Volt in Super Low Frequency mode
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CPUs, related to Intel Core 2 Duo T8300 (Socket P)
| Model |
Cores / Threads |
Freq. |
L2 cache |
TDP |
Features |
| Intel Core 2 Duo Mobile family, Socket P |
| Intel Core 2 Duo T9500 (Socket P) | 2 / 2 | 2.6 GHz | 6 MB | 35 Watt | SSE4, VT, ESS, TBT |
| Intel Core 2 Duo P9600 | 2 / 2 | 2.66 GHz | 6 MB | 25 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo T9550 (Socket P) | 2 / 2 | 2.66 GHz | 6 MB | 35 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo E8235 | 2 / 2 | 2.8 GHz | 6 MB | | SSE4, VT, ESS, TBT |
| Intel Core 2 Duo P9700 | 2 / 2 | 2.8 GHz | 6 MB | 28 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo T9600 (Socket P) | 2 / 2 | 2.8 GHz | 6 MB | 35 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo E8335 | 2 / 2 | 2.93 GHz | 6 MB | | SSE4, VT, ESS, TBT |
| Intel Core 2 Duo T9800 | 2 / 2 | 2.93 GHz | 6 MB | 35 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo E8435 | 2 / 2 | 3.06 GHz | 6 MB | | SSE4, VT, ESS, TBT |
| Intel Core 2 Duo T9900 (Socket P) | 2 / 2 | 3.06 GHz | 6 MB | 35 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo Mobile family, Core micro-architecture, Other sockets |
| Intel Core 2 Duo SP9600 | 2 / 2 | 2.53 GHz | 6 MB | 25 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo T9400 (BGA) | 2 / 2 | 2.53 GHz | 6 MB | 35 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo T9500 (BGA) | 2 / 2 | 2.6 GHz | 6 MB | 35 Watt | SSE4, VT, ESS, TBT |
| Intel Core 2 Duo T9550 (BGA) | 2 / 2 | 2.66 GHz | 6 MB | 35 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo T9600 (BGA) | 2 / 2 | 2.8 GHz | 6 MB | 35 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo T9900 (BGA) | 2 / 2 | 3.06 GHz | 6 MB | 35 Watt | SSE4, VT, TXT, ESS, TBT |
| Other families, Core micro-architecture, Socket P |
| Intel Mobile Celeron 925 | 1 / 1 | 2.3 GHz | 1 MB | 35 Watt | SSE4, VT, ESS, TBT |
| Intel Celeron M 570 | 1 / 1 | 2.26 GHz | 1 MB | 31 Watt | SSE4, VT, ESS, TBT |
| Intel Mobile Celeron T3500 | 2 / 2 | 2.1 GHz | 1 MB | 35 Watt | SSE4, VT, ESS, TBT |
| Intel Pentium T4500 | 2 / 2 | 2.3 GHz | 1 MB | 35 Watt | SSE4, VT, ESS, TBT |
| Intel Core 2 Quad Q9100 | 4 / 4 | 2.26 GHz | 12 MB | 45 Watt | SSE4, VT, ESS, TBT |
| Intel Core 2 Extreme QX9300 | 4 / 4 | 2.53 GHz | 12 MB | 45 Watt | SSE4, VT, ESS, TBT |
• Highlighted numbers and features indicate whether specific processor performs better or worse than Core 2 Duo T8300 (Socket P)
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• List of related CPUs is not complete.
• Features abbreviations:
SSE4 - SSE4 instructions VT - Virtualization TXT - Trusted Execution ESS - PowerNow! / Enhanced SpeedStep TBT - Dynamic Acceleration / Turbo Boost
CPU ID (1)
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Core 2 Duo Mobile T8300 CPU.
| Manufacturer: | Intel |
| CPU Family: | Core 2 Duo Mobile |
| Processor Number: | T8300 |
| Frequency: | 2400 MHz |
|
| Part number: | FF80577GG0563M |
| S-Spec Number: | |
| Comment: | |
| Submitted by: | Edward Jessen |
|
| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Core(TM)2 Duo CPU T8300 @ 2.40GHz |
| Cores: | 2 |
| Logical processors: | 2 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 10676 |
| Family: | 6 (06h) |
| Model: | 23 (017h) |
| Stepping: | 6 (06h) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
2 x 32 KB |
2 x 32 KB |
3 MB |
| Associativity: |
8-way set associative |
8-way set associative |
12-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
| Comments: |
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Shared between all cores |
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| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| SSE4.1 |
MONITOR/MWAIT |
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SYSENTER/SYSEXIT |
| |
| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| Intel Virtualization |
CPL qualified debug store |
| Turbo Boost |
Debug store |
| Enhanced SpeedStep |
Debugging extensions |
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Digital Thermal Sensor capability |
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LAHF/SAHF support in 64-bit mode |
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Machine check architecture |
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Machine check exception |
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Memory-type range registers |
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Model-specific registers |
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Page attribute table |
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Page global extension |
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Page-size extensions (4MB pages) |
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Pending break enable |
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Perfmon and Debug capability |
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Physical address extensions |
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Self-snoop |
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Thermal monitor |
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Thermal monitor 2 |
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Thermal monitor and software controlled clock facilities |
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Time stamp counter |
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Virtual 8086-mode enhancements |
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xTPR Update Control |
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