CPU-World logo News · Chips · Information · Forum · Links · About
BSP · CPU · FPU · MCU · SoC · Other ICs · Curiosities

Intel Core 2 Extreme Mobile X9100 AW80576ZH0836M

CPU » Intel » Core 2 families » Core 2 Extreme Mobile » X9100

Specifications

General information
TypeCPU / Microprocessor
Market segmentMobile
FamilyIntel Core 2 Extreme Mobile
Model number  ? X9100
CPU part numberAW80576ZH0836M is an OEM/tray microprocessor
Frequency (MHz)  ? 3067
Bus speed (MHz)  ? 1066
Clock multiplier  ? 11.5
Package478-pin micro-FCPGA
1.38" x 1.38" (3.5 cm x 3.5 cm)
SocketSocket P
Introduction dateJul 15, 2008
End-of-Life dateLast order date is March 25, 2011
Last shipment date is September 30, 2011
Price at introduction$851
 
S-spec numbers
  Production processors
Part number SLB48 SLGE7
AW80576ZH0836M++
 
Architecture / Microarchitecture
MicroarchitectureCore
PlatformMontevina
MontevinaPlus
Processor core  ? Penryn
Core steppings  ? C0 (SLB48)
E0 (SLGE7)
CPUID10676 (SLB48)
Manufacturing process0.045 micron
Data width64 bit
The number of cores2
The number of threads2
Floating Point UnitIntegrated
Level 1 cache size  ? 2 x 32 KB instruction caches
2 x 32 KB write-back data caches
Level 2 cache size  ? shared 6 MB
Features
  • MMX instruction set
  • SSE
  • SSE2
  • SSE3
  • Supplemental SSE3
  • SSE4.1  ? 
  • EM64T technology  ? 
  • Execute Disable Bit technology  ? 
  • Virtualization Technology  ? 
  • Intel Trusted Execution technology
Low power features
  • C1/AutoHALT, C1/MWAIT, C2, C3, C4 (with Enhanced Deep Sleep) and C6 core states
  • Stop Grant mode  ? 
  • Sleep mode  ? 
  • Deep Sleep mode  ? 
  • Deeper Sleep mode  ? 
  • Enhanced Deeper Sleep mode  ? 
  • Deep Power-Down state  ? 
  • Dynamic FSB Frequency switching  ? 
  • Enhanced SpeedStep technology  ? 
 
Electrical/Thermal parameters
V core (V)  ? 1 - 1.275
Minimum/Maximum operating temperature (°C)  ? 0 - 105
Minimum/Maximum power dissipation (W)  ? 7.45 (Deep Power-Down mode) / 70.87
Thermal Design Power (W)  ? 44
 
Notes on Intel AW80576ZH0836M
  • Bus frequency is 266 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 1066 MHz
  • Processor operates at 0.85 Volt - 1.1 Volt in Low Frequency mode
  • Processor operates at 0.8 Volt - 1 Volt in Super Low Frequency mode
  CPUs, related to Intel Core 2 Extreme X9100  

Model Cores /
Threads		 Freq. L2
cache		 TDP Features
Intel Core 2 Extreme Mobile family, Socket P
   Intel Core 2 Extreme X78002 / 22.6 GHz4 MB44 WattSSE4, VT, TXT, ESS, TBT
   Intel Core 2 Extreme X79002 / 22.8 GHz4 MB44 WattSSE4, VT, TXT, ESS, TBT
   Intel Core 2 Extreme X90002 / 22.8 GHz6 MB44 WattSSE4, VT, TXT, ESS, TBT
   Intel Core 2 Extreme QX93004 / 42.53 GHz12 MB45 WattSSE4, VT, TXT, ESS, TBT
Other families, Core micro-architecture, Socket P
   Intel Mobile Celeron 9001 / 12.2 GHz1 MB35 WattSSE4, VT, TXT, ESS
   Intel Mobile Celeron 9251 / 12.3 GHz1 MB35 WattSSE4, VT, TXT, ESS
   Intel Celeron M 5601 / 12.13 GHz1 MB31 WattSSE4, VT, TXT, ESS
   Intel Celeron M 5851 / 12.16 GHz1 MB31 WattSSE4, VT, TXT, ESS
   Intel Celeron M 5701 / 12.26 GHz1 MB31 WattSSE4, VT, TXT, ESS
   Intel Mobile Celeron T3100 (Socket P)2 / 21.9 GHz1 MB35 WattSSE4, VT, TXT, ESS
   Intel Mobile Celeron T33002 / 22 GHz1 MB35 WattSSE4, VT, TXT, ESS
   Intel Mobile Celeron T35002 / 22.1 GHz1 MB35 WattSSE4, VT, TXT, ESS
   Intel Pentium T44002 / 22.2 GHz1 MB35 WattSSE4, VT, TXT, ESS
   Intel Pentium T45002 / 22.3 GHz1 MB35 WattSSE4, VT, TXT, ESS
   Intel Core 2 Duo E84352 / 23.06 GHz6 MB SSE4, VT, TXT, ESS
   Intel Core 2 Duo T9900 (Socket P)2 / 23.06 GHz6 MB35 WattSSE4, VT, TXT, ESS, TBT
   Intel Core 2 Quad Q90004 / 42 GHz6 MB45 WattSSE4, VT, TXT, ESS, TBT
   Intel Core 2 Quad Q91004 / 42.26 GHz12 MB45 WattSSE4, VT, TXT, ESS, TBT

 • Highlighted numbers and features indicate whether specific processor performs better or worse than Core 2 Extreme X9100

 • Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)

 • List of related CPUs is not complete.

 • Features abbreviations:

SSE4 - SSE4 instructions
VT - Virtualization
TXT - Trusted Execution
ESS - PowerNow! / Enhanced SpeedStep
TBT - Dynamic Acceleration / Turbo Boost

Pictures (0)

News


Intel discontinues mobile Q9000, Q9100, X9100 and QX9300 CPUs
Sep 11, 2010: In two recently published Product Change Notification documents, Intel informed its customers about planned discontinuance of Core 2 Quad Q9000 and Q9100, and Core 2 Extreme X9100 and QX9300 microprocessors. The last date, when these models can be ordered, is March 25, 2011, and the last shipment date of OEM version of these processors is September 30, 2011.



Intel to discontinue Core 2 Mobile processors
Jun 09, 2010: Recently Engadget posted slides from a leaked Intel mobile processors roadmap, covering the second half of this year and the first half of the next year. That document contained not only information about future new mobile processors, but also useful data on discontinued Core 2 Mobile CPUs.


CPU ID (1)

NOTE: CPU ID information below was taken from one CPU and may include features that are not present in all different steppings of the Intel Core 2 Extreme Mobile X9100 CPU.

Manufacturer:Intel
CPU Family:Core 2 Extreme Mobile
Processor Number:X9100
Frequency:3059 MHz
Part number:
AW80576ZH0836M
S-Spec Number:
Comment:
Submitted by:Charlie Thompson
General information
Vendor:GenuineIntel
Processor name (BIOS):Intel(R) Core(TM)2 Extreme CPU X9100 @ 3.06GHz
Cores:2
Logical processors:2
Processor type:Original OEM Processor
CPUID signature:10676
Family: 6 (06h)
Model:23 (017h)
Stepping: 6 (06h)
TLB/Cache details:64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache: L1 data L1 instruction L2
Size: 2 x 32 KB 2 x 32 KB 6 MB
Associativity: 8-way set
associative		 8-way set
associative		 24-way set
associative
Line size: 64 bytes 64 bytes 64 bytes
Comments:     Shared between all cores
 
Instruction set extensionsAdditional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
SSSE3 FXSAVE/FXRSTORE
SSE4.1 MONITOR/MWAIT
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
64-bit / Intel 64 64-bit debug store
NX bit/XD-bit Advanced programmable interrupt controller
Intel Virtualization CPL qualified debug store
Enhanced SpeedStep Debug store
  Debugging extensions
  Digital Thermal Sensor capability
  LAHF/SAHF support in 64-bit mode
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Perfmon and Debug capability
  Physical address extensions
  Self-snoop
  Thermal monitor
  Thermal monitor 2
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control

Comments (0)

Last modified: 5 Feb 2012
Terms and Conditions · Privacy Policy · Contact Us (c) Copyright 2003 - 2010 Gennadiy Shvets

Search CPU-World

Search site contents:

Identify part

Identify CPU, FPU or MCU:

Related Links

Architecture
Identification
Pinouts
Support chips
Price Chart

Find CPUs

Find Core 2 Extreme Mobile CPUs with:

Same socket