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Intel Core 2 Extreme QX6850 HH80562XJ0808M (BX80562QX6850)
Specifications
Tools
Intel Core 2 Extreme QX6850 specifications
| General information |
| Type | CPU / Microprocessor |
| Market segment | Desktop |
| Family | Intel Core 2 Extreme |
| Model number ? | QX6850 |
| CPU part numbers | HH80562XJ0808M is an OEM/tray microprocessor BX80562QX6850 is a boxed microprocessor |
| Frequency ? | 3000 MHz |
| Bus speed ? | 1333 MHz |
| Clock multiplier ? | 9 |
| Package | 775-land Flip-Chip Land Grid Array (FC-LGA6)
1.48" x 1.48" (3.75 cm x 3.75 cm) |
| Socket | Socket 775 / LGA775 / T |
| Introduction date | Jul 16, 2007 |
| Price at introduction | $999 |
| | | S-spec numbers |
| |
ES/QS processors |
Production processors |
| Part number |
QXTN |
SLAFN |
| BX80562QX6850 | | + |
| HH80562XJ0808M | + | + |
|
| | | Architecture / Microarchitecture |
| Microarchitecture | Core |
| Processor core ? | Kentsfield |
| Core stepping ? | G0 (SLAFN) |
| CPUID | 6FB (SLAFN) |
| Manufacturing process | 0.065 micron
582 million transistors |
| Die size | 286mm2 |
| Data width | 64 bit |
| The number of cores | 4 |
| The number of threads | 4 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 4 x 32 KB instruction caches
4 x 32 KB data caches |
| Level 2 cache size ? | 2 x 4 MB caches (each L2 cache is shared between 2 cores) |
| Multiprocessing | Uniprocessor |
| Features | - MMX instructions
- SSE / Streaming SIMD Extensions
- SSE2 / Streaming SIMD Extensions 2
- SSE3 / Streaming SIMD Extensions 3
- SSSE3 / Supplemental Streaming SIMD Extensions 3
- EM64T / Extended Memory 64 technology / Intel 64 ?
- VT / Virtualization technology ?
- NX / XD / Execute disable bit ?
|
| Low power features | - Enhanced SpeedStep technology ?
- Stop Grant state ?
- Halt state
- Extended Halt state
|
| | | Electrical / Thermal parameters |
| V core ? | 0.85V - 1.5V |
| Maximum operating temperature ? | 64.5°C |
| Maximum power dissipation ? | 167.13 Watt |
| Thermal Design Power ? | 130 Watt |
| |
| Notes on Intel HH80562XJ0808M |
- Binary compatible with 32-bit x86 software
- Bus frequency is 333 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 1333 MHz
|
CPUs, related to Intel Core 2 Extreme QX6850
| Model |
Cores / Threads |
Freq. |
L2 cache |
Multi- processing |
TDP |
Features |
| Intel Core 2 Extreme family, Socket 775 |
| Core 2 Extreme X6800 | 2 / 2 | 2.93 GHz | 4 MB | 1 | 75 Watt | VT, ESS |
| Core 2 Extreme QX6700 | 4 / 4 | 2.66 GHz | 8 MB | 1 | 130 Watt | VT, ESS |
| Core 2 Extreme QX6800 | 4 / 4 | 2.93 GHz | 8 MB | 1 | 130 Watt | VT, ESS |
| Core 2 Extreme QX6850 | 4 / 4 | 3 GHz | 8 MB | 1 | 130 Watt | VT, ESS |
| Core 2 Extreme QX9650 | 4 / 4 | 3 GHz | 12 MB | 1 | 130 Watt | VT, ESS |
| Core 2 Extreme QX9770 | 4 / 4 | 3.2 GHz | 12 MB | 1 | 136 Watt | VT, ESS |
| Intel Core 2 Extreme family, Core micro-architecture, Other sockets |
| Core 2 Extreme QX9775 | 4 / 4 | 3.2 GHz | 12 MB | 2 | 150 Watt | VT, ESS |
| Other families, Core micro-architecture, Socket 775 |
| Celeron 440 | 1 / 1 | 2 GHz | 512 KB | | 35 Watt | VT, ESS |
| Celeron 450 | 1 / 1 | 2.2 GHz | 512 KB | | 35 Watt | VT, ESS |
| Celeron E3400 | 2 / 2 | 2.6 GHz | 1 MB | 1 | 65 Watt | VT, ESS |
| Celeron E3500 | 2 / 2 | 2.7 GHz | 1 MB | 1 | 65 Watt | VT, ESS |
| Pentium E5800 | 2 / 2 | 3.2 GHz | 2 MB | 1 | 65 Watt | VT, ESS |
| Pentium E6800 | 2 / 2 | 3.33 GHz | 2 MB | 1 | 65 Watt | VT, ESS |
| Core 2 Duo E8500 | 2 / 2 | 3.16 GHz | 6 MB | 1 | 65 Watt | VT, TXT, ESS |
| Core 2 Duo E8600 | 2 / 2 | 3.33 GHz | 6 MB | 1 | 65 Watt | VT, TXT, ESS |
| Core 2 Quad Q9705 | 4 / 4 | 3.16 GHz | 6 MB | 1 | 95 Watt | VT, TXT, ESS |
| Core 2 Quad Q9650 | 4 / 4 | 3 GHz | 12 MB | 1 | 95 Watt | VT, TXT, ESS |
• Highlighted numbers and features indicate whether specific processor performs better or worse than Core 2 Extreme QX6850
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• List of related CPUs is not complete.
• Features abbreviations:
VT - Virtualization TXT - Trusted Execution ESS - PowerNow! / Enhanced SpeedStep
FAQ
Q: I have an Intel Core 2 Extreme QX6850 processor. Is it possible to upgrade it?
A: Probably yes. CPU compatibility is determined by your motherboard. Please check CPU-Upgrade.com website for CPU support list for your board.
Intel QX6850 Overclocking
Sorry, overclocking information is not available at this time.
CPU ID (2)
CPUID Tools
CPUID features of Intel QX6850
NOTE: The CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Core 2 Extreme QX6850 CPU.
| Manufacturer: | Intel |
| CPU Family: | Core 2 Extreme |
| Processor Number: | QX6850 |
| Frequency: | 3000 MHz |
|
| Part number: | HH80562XJ0808M |
| S-Spec Number: | |
| Comment: | |
| Submitted by: | |
|
| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Core(TM)2 Extreme CPU Q6850 @ 3.00GHz |
| Cores: | 4 |
| Logical processors: | 4 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 6FB |
| Family: | 6 (06h) |
| Model: | 15 (0Fh) |
| Stepping: | 11 (0Bh) |
| TLB/Cache details: | 3rd-level cache: 4-MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0Fh, Model 06h), 2nd-level cache: 4-MB, 16-way set associative, 64-byte line size
64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
4 x 32 KB |
4 x 32 KB |
2 x 4 MB |
| Associativity: |
8-way set associative |
8-way set associative |
16-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
| Comments: |
Direct-mapped |
Direct-mapped |
Non-inclusive Direct-mapped 1 cache per 2 cores |
| |
| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
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MONITOR/MWAIT |
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SYSENTER/SYSEXIT |
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| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| Intel Virtualization |
CPL qualified debug store |
| Enhanced SpeedStep |
Debug store |
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Debugging extensions |
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Digital Thermal Sensor capability |
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LAHF / SAHF support in 64-bit mode |
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Machine check architecture |
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Machine check exception |
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Memory-type range registers |
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Model-specific registers |
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Page attribute table |
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Page global extension |
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Page-size extensions (4MB pages) |
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Pending break enable |
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Perfmon and Debug capability |
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Physical address extensions |
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Self-snoop |
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Thermal monitor |
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Thermal monitor 2 |
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Thermal monitor and software controlled clock facilities |
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Time stamp counter |
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Virtual 8086-mode enhancements |
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xTPR Update Control |
Comments (0)
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