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Intel Core 2 Extreme QX9650 EU80569XJ080NL (BX80569QX9650)
Specifications
Tools
Intel Core 2 Extreme QX9650 specifications
| General information |
| Type | CPU / Microprocessor |
| Market segment | Desktop |
| Family | Intel Core 2 Extreme |
| Model number ? | QX9650 |
| CPU part numbers | EU80569XJ080NL is an OEM/tray microprocessor BX80569QX9650 is a boxed microprocessor |
| Frequency ? | 3000 MHz |
| Bus speed ? | 1333 MHz |
| Clock multiplier ? | 9 |
| Package | 775-land Flip-Chip Land Grid Array (FC-LGA8)
1.48" x 1.48" (3.75 cm x 3.75 cm) |
| Socket | Socket 775 / LGA775 / T |
| Introduction date | Nov 11, 2007 |
| Price at introduction | $999 |
| | | S-spec numbers |
| |
ES/QS processors |
Production processors |
| Part number |
Q7UE |
QEFX |
SLAN3 |
SLAWN |
| BX80569QX9650 | | | + | + |
| EU80569XJ080NL | + | + | + | + |
|
| | | Architecture / Microarchitecture |
| Microarchitecture | Core |
| Processor core ? | Yorkfield |
| Core steppings ? | C0 (Q7UE, SLAN3) C1 (QEFX, SLAWN) |
| CPUIDs | 676 (Q7UE) 677 (QEFX) 10676 (SLAN3) 10677 (SLAWN) |
| Manufacturing process | 0.045 micron
820 million transistors |
| Die size | 214mm2 |
| Data width | 64 bit |
| The number of cores | 4 |
| The number of threads | 4 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 4 x 32 KB instruction caches
4 x 32 KB data caches |
| Level 2 cache size ? | 2 x 6 MB 12-way set associative caches (each L2 cache is shared between 2 cores) |
| Multiprocessing | Uniprocessor |
| Features | - MMX instructions
- SSE / Streaming SIMD Extensions
- SSE2 / Streaming SIMD Extensions 2
- SSE3 / Streaming SIMD Extensions 3
- SSSE3 / Supplemental Streaming SIMD Extensions 3
- EM64T / Extended Memory 64 technology / Intel 64 ?
- VT / Virtualization technology ?
- NX / XD / Execute disable bit ?
- SSE4.1 / Streaming SIMD Extensions 4.1 ?
|
| Low power features | - Enhanced SpeedStep technology ?
- Stop Grant state ?
- Halt state
- Extended Halt state
- Extended Stop Grant State
- Sleep state ?
- Deep Sleep state ?
- Deeper Sleep state ?
|
| | | Electrical / Thermal parameters |
| V core ? | 0.85V - 1.3625V |
| Minimum/Maximum operating temperature ? | 5°C - 64.5°C |
| Minimum/Maximum power dissipation ? | 16 Watt (TDP in extended HALT state) / 159.17 Watt |
| Thermal Design Power ? | 130 Watt |
| |
| Notes on Intel EU80569XJ080NL |
- Binary compatible with 32-bit x86 software
- Bus frequency is 333 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 1333 MHz
|
CPUs, related to Intel Core 2 Extreme QX9650
| Model |
Cores / Threads |
Freq. |
L2 cache |
Multi- processing |
TDP |
Features |
| Intel Core 2 Extreme family, Socket 775 |
| Core 2 Extreme X6800 | 2 / 2 | 2.93 GHz | 4 MB | 1 | 75 Watt | VT, ESS |
| Core 2 Extreme QX6700 | 4 / 4 | 2.66 GHz | 8 MB | 1 | 130 Watt | VT, ESS |
| Core 2 Extreme QX6800 | 4 / 4 | 2.93 GHz | 8 MB | 1 | 130 Watt | VT, ESS |
| Core 2 Extreme QX6850 | 4 / 4 | 3 GHz | 8 MB | 1 | 130 Watt | VT, ESS |
| Core 2 Extreme QX9650 | 4 / 4 | 3 GHz | 12 MB | 1 | 130 Watt | VT, ESS |
| Core 2 Extreme QX9770 | 4 / 4 | 3.2 GHz | 12 MB | 1 | 136 Watt | VT, ESS |
| Intel Core 2 Extreme family, Core micro-architecture, Other sockets |
| Core 2 Extreme QX9775 | 4 / 4 | 3.2 GHz | 12 MB | 2 | 150 Watt | VT, ESS |
| Other families, Core micro-architecture, Socket 775 |
| Celeron 440 | 1 / 1 | 2 GHz | 512 KB | | 35 Watt | VT, ESS |
| Celeron 450 | 1 / 1 | 2.2 GHz | 512 KB | | 35 Watt | VT, ESS |
| Celeron E3400 | 2 / 2 | 2.6 GHz | 1 MB | 1 | 65 Watt | VT, ESS |
| Celeron E3500 | 2 / 2 | 2.7 GHz | 1 MB | 1 | 65 Watt | VT, ESS |
| Pentium E5800 | 2 / 2 | 3.2 GHz | 2 MB | 1 | 65 Watt | VT, ESS |
| Pentium E6800 | 2 / 2 | 3.33 GHz | 2 MB | 1 | 65 Watt | VT, ESS |
| Core 2 Duo E8500 | 2 / 2 | 3.16 GHz | 6 MB | 1 | 65 Watt | VT, TXT, ESS |
| Core 2 Duo E8600 | 2 / 2 | 3.33 GHz | 6 MB | 1 | 65 Watt | VT, TXT, ESS |
| Core 2 Quad Q9705 | 4 / 4 | 3.16 GHz | 6 MB | 1 | 95 Watt | VT, TXT, ESS |
| Core 2 Quad Q9650 | 4 / 4 | 3 GHz | 12 MB | 1 | 95 Watt | VT, TXT, ESS |
• Highlighted numbers and features indicate whether specific processor performs better or worse than Core 2 Extreme QX9650
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• List of related CPUs is not complete.
• Features abbreviations:
VT - Virtualization TXT - Trusted Execution ESS - PowerNow! / Enhanced SpeedStep
FAQ
Q: Can I upgrade my QX9650 microprocessor?
A: Probably yes. CPU compatibility is determined by your motherboard. Please see CPU-Upgrade.com resource for CPU support list for your board.
Intel QX9650 Overclocking
Sorry, overclocking information is not available at this time.
CPU ID (4)
CPUID Tools
CPUID features of Intel X9650
NOTE: The CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Core 2 Extreme X9650 CPU.
| Manufacturer: | Intel |
| CPU Family: | Core 2 Extreme |
| Processor Number: | X9650 |
| Frequency: | 2999 MHz |
|
| Part number: | EU80569XJ080NL |
| S-Spec Number: | |
| Comment: | |
| Submitted by: | Bernhard |
|
| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Core(TM)2 Extreme CPU X9650 @ 3.00GHz |
| Cores: | 4 |
| Logical processors: | 4 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 10677 |
| Family: | 6 (06h) |
| Model: | 23 (017h) |
| Stepping: | 7 (07h) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
4 x 32 KB |
4 x 32 KB |
2 x 6 MB |
| Associativity: |
8-way set associative |
8-way set associative |
24-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
| Comments: |
Direct-mapped |
Direct-mapped |
Non-inclusive Direct-mapped 1 cache per 2 cores |
| |
| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| SSE4.1 |
MONITOR/MWAIT |
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SYSENTER/SYSEXIT |
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| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| Intel Virtualization |
Advanced programmable interrupt controller |
| Enhanced SpeedStep |
CPL qualified debug store |
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Debug store |
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Debugging extensions |
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Digital Thermal Sensor capability |
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LAHF / SAHF support in 64-bit mode |
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Machine check architecture |
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Machine check exception |
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Memory-type range registers |
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Model-specific registers |
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Page attribute table |
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Page global extension |
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Page-size extensions (4MB pages) |
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Pending break enable |
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Perfmon and Debug capability |
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Physical address extensions |
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Self-snoop |
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Thermal monitor |
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Thermal monitor 2 |
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Thermal monitor and software controlled clock facilities |
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Time stamp counter |
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Virtual 8086-mode enhancements |
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xTPR Update Control |
Comments (1)
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Intel Core 2 Extreme QX9650 review, or your experience with the microprocessor.
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pdn
PDN for QX9650 is in the first quater 2009
and will phase out of the market in the second
quarter