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Intel Core 2 Quad Mobile Q9000 AW80581GH0416M (BX80581Q9000)
Specifications
| General information |
| Type | CPU / Microprocessor |
| Market segment | Mobile |
| Family | Intel Core 2 Quad Mobile |
| Model number ? | Q9000 |
| CPU part numbers | AW80581GH0416M is an OEM/tray microprocessor BX80581Q9000 is a boxed microprocessor |
| Frequency (MHz) ? | 2000 |
| Bus speed (MHz) ? | 1066 |
| Clock multiplier ? | 7.5 |
| Package | 478-pin micro-FCPGA
1.38" x 1.38" (3.5 cm x 3.5 cm) |
| Socket | Socket P |
| Introduction date | Dec 28, 2008 |
| End-of-Life date | Last order date is March 25, 2011
Last shipment date is September 30, 2011 |
| Price at introduction | $348 |
| | | S-spec numbers |
| |
ES/QS processors |
Production processors |
| Part number |
QJTA |
SLGEJ |
| AW80581GH0416M | + | + |
| BX80581Q9000 | | + |
|
| | | Architecture / Microarchitecture |
| Microarchitecture | Core |
| Platform | Montevina
MontevinaPlus |
| Core stepping ? | E0 (SLGEJ) |
| CPUID | 10676 (SLGEJ) |
| Manufacturing process | 0.045 micron |
| Data width | 64 bit |
| The number of cores | 4 |
| The number of threads | 4 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 4 x 32 KB instruction caches
4 x 32 KB write-back data caches |
| Level 2 cache size ? | shared 6 MB |
| Features | - MMX instruction set
- SSE
- SSE2
- SSE3
- Supplemental SSE3
- SSE4.1 ?
- EM64T technology ?
- Execute Disable Bit technology ?
- Virtualization Technology ?
- Dual Dynamic Acceleration ?
|
| Low power features | - C1/AutoHALT, C1/MWAIT, C2, C3 and C4 core states
- Stop Grant mode ?
- Sleep mode ?
- Deep Sleep mode ?
- Deeper Sleep mode ?
- FSB low-power enhancements
- Enhanced SpeedStep technology ?
|
| | | Electrical/Thermal parameters |
| V core (V) ? | 0.9 - 1.25 |
| Minimum/Maximum operating temperature (°C) ? | 0 - 100 |
| Minimum/Maximum power dissipation (W) ? | 16.54 (Deeper Sleep mode) / 74.35 |
| Thermal Design Power (W) ? | 45 |
| |
| Notes on Intel AW80581GH0416M |
- Bus frequency is 266 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 1066 MHz
- Processor operates at 0.85 Volt - 1.1 Volt in Low Frequency mode
|
CPUs, related to Intel Core 2 Quad Q9000
| Model |
Cores / Threads |
Freq. |
L2 cache |
TDP |
Features |
| Intel Core 2 Quad Mobile family, Socket P |
| Intel Core 2 Quad Q9100 | 4 / 4 | 2.26 GHz | 12 MB | 45 Watt | SSE4, VT, ESS, TBT |
| Other families, Core micro-architecture, Socket P |
| Intel Mobile Celeron 900 | 1 / 1 | 2.2 GHz | 1 MB | 35 Watt | SSE4, VT, ESS, TBT |
| Intel Mobile Celeron 925 | 1 / 1 | 2.3 GHz | 1 MB | 35 Watt | SSE4, VT, ESS, TBT |
| Intel Celeron M 560 | 1 / 1 | 2.13 GHz | 1 MB | 31 Watt | SSE4, VT, ESS, TBT |
| Intel Celeron M 585 | 1 / 1 | 2.16 GHz | 1 MB | 31 Watt | SSE4, VT, ESS, TBT |
| Intel Celeron M 570 | 1 / 1 | 2.26 GHz | 1 MB | 31 Watt | SSE4, VT, ESS, TBT |
| Intel Mobile Celeron T3100 (Socket P) | 2 / 2 | 1.9 GHz | 1 MB | 35 Watt | SSE4, VT, ESS, TBT |
| Intel Mobile Celeron T3300 | 2 / 2 | 2 GHz | 1 MB | 35 Watt | SSE4, VT, ESS, TBT |
| Intel Mobile Celeron T3500 | 2 / 2 | 2.1 GHz | 1 MB | 35 Watt | SSE4, VT, ESS, TBT |
| Intel Pentium T3400 | 2 / 2 | 2.16 GHz | 1 MB | 35 Watt | SSE4, VT, ESS, TBT |
| Intel Pentium T4400 | 2 / 2 | 2.2 GHz | 1 MB | 35 Watt | SSE4, VT, ESS, TBT |
| Intel Pentium T4500 | 2 / 2 | 2.3 GHz | 1 MB | 35 Watt | SSE4, VT, ESS, TBT |
| Intel Core 2 Extreme X9000 | 2 / 2 | 2.8 GHz | 6 MB | 44 Watt | SSE4, VT, ESS, TBT |
| Intel Core 2 Duo T9800 | 2 / 2 | 2.93 GHz | 6 MB | 35 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo E8435 | 2 / 2 | 3.06 GHz | 6 MB | | SSE4, VT, ESS, TBT |
| Intel Core 2 Extreme X9100 | 2 / 2 | 3.06 GHz | 6 MB | 44 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Duo T9900 (Socket P) | 2 / 2 | 3.06 GHz | 6 MB | 35 Watt | SSE4, VT, TXT, ESS, TBT |
| Intel Core 2 Extreme QX9300 | 4 / 4 | 2.53 GHz | 12 MB | 45 Watt | SSE4, VT, ESS, TBT |
• Highlighted numbers and features indicate whether specific processor performs better or worse than Core 2 Quad Q9000
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• List of related CPUs is not complete.
• Features abbreviations:
SSE4 - SSE4 instructions VT - Virtualization TXT - Trusted Execution ESS - PowerNow! / Enhanced SpeedStep TBT - Dynamic Acceleration / Turbo Boost
News
Sep 11, 2010: In two recently published Product Change Notification documents,
Intel informed its customers about planned discontinuance of Core 2
Quad Q9000 and Q9100, and Core 2 Extreme X9100 and QX9300
microprocessors. The last date, when these models can be ordered, is
March 25, 2011, and the last shipment date of OEM version of these
processors is September 30, 2011.
Jun 09, 2010: Recently Engadget posted slides from a leaked Intel mobile
processors roadmap, covering the second half of this year and the first
half of the next year. That document contained not only information
about future new mobile processors, but also useful data on
discontinued Core 2 Mobile CPUs.
CPU ID (1)
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Core 2 Quad Q9000 CPU.
| Manufacturer: | Intel |
| CPU Family: | Core 2 Quad |
| Processor Number: | Q9000 |
| Frequency: | 1999 MHz |
|
| Part number: | AW80581GH0416M |
| S-Spec Number: | |
| Comment: | |
| Submitted by: | |
|
| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Core(TM)2 Quad CPU Q9000 @ 2.00GHz |
| Cores: | 4 |
| Logical processors: | 4 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 1067A |
| Family: | 6 (06h) |
| Model: | 23 (017h) |
| Stepping: | 10 (0Ah) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
4 x 32 KB |
4 x 32 KB |
2 x 3 MB |
| Associativity: |
8-way set associative |
8-way set associative |
12-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
| Comments: |
|
|
1 cache per 2 cores |
| |
| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| SSE4.1 |
MONITOR/MWAIT |
| |
SYSENTER/SYSEXIT |
| |
XSAVE/XRESTORE states |
| |
XSETBV/XGETBV are enabled |
| |
| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| Intel Virtualization |
CPL qualified debug store |
| Intel Trusted Execution technology |
Debug store |
| Enhanced SpeedStep |
Debugging extensions |
| |
Digital Thermal Sensor capability |
| |
LAHF/SAHF support in 64-bit mode |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
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Model-specific registers |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Pending break enable |
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Perfmon and Debug capability |
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Physical address extensions |
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Self-snoop |
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Thermal monitor |
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Thermal monitor 2 |
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Thermal monitor and software controlled clock facilities |
| |
Time stamp counter |
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Virtual 8086-mode enhancements |
| |
xTPR Update Control |
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Find CPUs
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