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Intel Core 2 Quad Q9450 EU80569PJ067N (BX80569Q9450 / BXC80569Q9450)
Specifications
| General information |
| Type | CPU / Microprocessor |
| Market segment | Desktop |
| Family | Intel Core 2 Quad |
| Model number ? | Q9450 |
| CPU part numbers | EU80569PJ067N is an OEM/tray microprocessor BX80569Q9450 is a boxed microprocessor BXC80569Q9450 is a boxed microprocessor |
| Frequency (MHz) ? | 2667 |
| Bus speed (MHz) ? | 1333 |
| Clock multiplier ? | 8 |
| Package | 775-land Flip-Chip Land Grid Array (FC-LGA8)
1.48" x 1.48" (3.75 cm x 3.75 cm) |
| Socket | Socket 775 (LGA775) |
| Introduction date | Jan 7, 2008 |
| Price at introduction | $316 |
| | | S-spec numbers |
| |
ES/QS processors |
Production processors |
| Part number |
Q7UP |
SLAWR |
| BX80569Q9450 | | + |
| BXC80569Q9450 | | + |
| EU80569PJ067N | + | + |
|
| | | Architecture / Microarchitecture |
| Microarchitecture | Core |
| Processor core ? | Yorkfield |
| Core steppings ? | C0 (Q7UP) C1 (SLAWR) |
| CPUID | 10677 (SLAWR) |
| Manufacturing process | 0.045 micron |
| Data width | 64 bit |
| The number of cores | 4 |
| The number of threads | 4 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 4 x 32 KB instruction caches
4 x 32 KB data caches |
| Level 2 cache size ? | 2 x 6 MB 12-way set associative caches (each L2 cache is shared between 2 cores) |
| Multiprocessing | Uniprocessor |
| Features | - MMX instruction set
- SSE
- SSE2
- SSE3
- Supplemental SSE3
- EM64T technology ?
- Virtualization Technology ?
- Execute Disable Bit technology ?
- SSE4.1 ?
- Trusted Execution technology
|
| Low power features | - Enhanced SpeedStep technology ?
- Stop Grant state ?
- Halt state
- Extended Halt state
- Extended Stop Grant State
- Sleep state ?
- Deep Sleep state ?
- Deeper Sleep state ?
|
| | | Electrical/Thermal parameters |
| V core (V) ? | 0.85 - 1.3625 |
| Minimum/Maximum operating temperature (°C) ? | 5 - 71.4 |
| Minimum/Maximum power dissipation (W) ? | 12 (TDP in extended HALT state) / 132.48 |
| Thermal Design Power (W) ? | 95 |
| |
| Notes on Intel EU80569PJ067N |
- Binary compatible with 32-bit x86 software
- Bus frequency is 333 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 1333 MHz
- BXC80569Q9450 is a Chinese version
|
CPUs, related to Intel Core 2 Quad Q9450
| Model |
Cores / Threads |
Freq. |
L2 cache |
TDP |
Features |
| Intel Core 2 Quad family, Socket 775 |
| Intel Core 2 Quad Q6700 | 4 / 4 | 2.66 GHz | 8 MB | 95 Watt | SSE4, VT, TXT, ESS |
| Intel Core 2 Quad Q9500 | 4 / 4 | 2.83 GHz | 6 MB | 95 Watt | SSE4, VT, TXT, ESS |
| Intel Core 2 Quad Q9505 | 4 / 4 | 2.83 GHz | 6 MB | 95 Watt | SSE4, VT, TXT, ESS |
| Intel Core 2 Quad Q9505S | 4 / 4 | 2.83 GHz | 6 MB | 65 Watt | SSE4, VT, TXT, ESS |
| Intel Core 2 Quad Q9450S | 4 / 4 | 2.66 GHz | 12 MB | 65 Watt | SSE4, VT, TXT, ESS |
| Intel Core 2 Quad Q9550 | 4 / 4 | 2.83 GHz | 12 MB | 95 Watt | SSE4, VT, TXT, ESS |
| Intel Core 2 Quad Q9550S | 4 / 4 | 2.83 GHz | 12 MB | 65 Watt | SSE4, VT, TXT, ESS |
| Intel Core 2 Quad Q9700 | 4 / 4 | 3.16 GHz | 6 MB | 95 Watt | SSE4, VT, TXT, ESS |
| Intel Core 2 Quad Q9705 | 4 / 4 | 3.16 GHz | 6 MB | 95 Watt | SSE4, VT, TXT, ESS |
| Intel Core 2 Quad Q9650 | 4 / 4 | 3 GHz | 12 MB | 95 Watt | SSE4, VT, TXT, ESS |
| Other families, Core micro-architecture, Socket 775 |
| Intel Celeron 440 | 1 / 1 | 2 GHz | 512 KB | 35 Watt | SSE4, VT, TXT, ESS |
| Intel Celeron 450 | 1 / 1 | 2.2 GHz | 512 KB | 35 Watt | SSE4, VT, TXT, ESS |
| Intel Celeron E3500 | 2 / 2 | 2.7 GHz | 1 MB | 65 Watt | SSE4, VT, TXT, ESS |
| Intel Pentium E6800 | 2 / 2 | 3.33 GHz | 2 MB | 65 Watt | SSE4, VT, TXT, ESS |
| Intel Core 2 Duo E8500 | 2 / 2 | 3.16 GHz | 6 MB | 65 Watt | SSE4, VT, TXT, ESS |
| Intel Core 2 Duo E8600 | 2 / 2 | 3.33 GHz | 6 MB | 65 Watt | SSE4, VT, TXT, ESS |
| Intel Core 2 Extreme QX9650 | 4 / 4 | 3 GHz | 12 MB | 130 Watt | SSE4, VT, TXT, ESS |
| Intel Core 2 Extreme QX9770 | 4 / 4 | 3.2 GHz | 12 MB | 136 Watt | SSE4, VT, TXT, ESS |
• Highlighted numbers and features indicate whether specific processor performs better or worse than Core 2 Quad Q9450
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• List of related CPUs is not complete.
• Features abbreviations:
SSE4 - SSE4 instructions VT - Virtualization TXT - Trusted Execution ESS - PowerNow! / Enhanced SpeedStep
CPU ID (3)
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Core 2 Quad Q9450 CPU.
| Manufacturer: | Intel |
| CPU Family: | Core 2 Quad |
| Processor Number: | Q9450 |
| Frequency: | 2799 MHz |
|
| Part number: | EU80569PJ067N |
| S-Spec Number: | |
| Comment: | |
| Submitted by: | |
|
| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Core(TM)2 Quad CPU Q9450 @ 2.66GHz |
| Cores: | 4 |
| Logical processors: | 4 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 10677 |
| Family: | 6 (06h) |
| Model: | 23 (017h) |
| Stepping: | 7 (07h) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
4 x 32 KB |
4 x 32 KB |
2 x 6 MB |
| Associativity: |
8-way set associative |
8-way set associative |
24-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
| Comments: |
|
|
1 cache per 2 cores |
| |
| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| SSE4.1 |
MONITOR/MWAIT |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| Intel Virtualization |
Advanced programmable interrupt controller |
| Intel Trusted Execution technology |
CPL qualified debug store |
| Enhanced SpeedStep |
Debug store |
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Debugging extensions |
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Digital Thermal Sensor capability |
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LAHF/SAHF support in 64-bit mode |
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Machine check architecture |
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Machine check exception |
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Memory-type range registers |
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Model-specific registers |
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Page attribute table |
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Page global extension |
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Page-size extensions (4MB pages) |
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Pending break enable |
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Perfmon and Debug capability |
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Physical address extensions |
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Self-snoop |
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Thermal monitor |
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Thermal monitor 2 |
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Thermal monitor and software controlled clock facilities |
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Time stamp counter |
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Virtual 8086-mode enhancements |
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xTPR Update Control |
Our CPUID database has 3 records for this microprocessor. See all submitted records.
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