CPU Information
The first Core i5 microprocessor, i5-750, was released 10 months after official launch of Nehalem micro-architecture and Core i7 family in November 2008. The i5-750 is based on newer Lynnfield core, which replaced Quick Path interconnect with slower Direct Media Interface, reduced the number of memory channels from three to two, and integrated PCI Express interface on die. The i5-750, and so far all other members of the Core i5 family, were manufactured in smaller package than Core i7-9xx Bloomfield processors. The package size of i5-750 is identical to the size of socket 775 packages, although it has 1156, or 50%, more contacts. New 1156-land package has two notches, which provide proper CPU orientation when the CPU is inserted into socket 1156, and prevent the CPU from inserting into socket 775 boards. Even with somewhat crippled features, performance of the i5-750 is comparable to more expensive Core i7-9xx family and top AMD Phenom II X4 CPUs. In office applications the i5-750 is as good as Core i7-920, and from 0 to 10% faster than Phenom II 965. In media applications performance of this and other Core i7 and Phenom II processors is very dependent on application. In some applications the i5-750 is as fast as the i7-920 and up to 15% faster than the Phenom II X4 965. In other applications the i5-750 is 25% slower than the i7-920 and up to 5% slower than the Phenom II. In games the i5-750 performs very close to both i7-920 and Phenom II 965.
| General information |
| Type | CPU / Microprocessor |
| Family | Intel Core i5 |
| Model number ? | I5-750 |
| CPU part number | BV80605001911AP (Q3AN, SLBLC) |
| Box part numbers | BX80605I5750 (SLBLC)
BXC80605I5750 (SLBLC) |
| Frequency (MHz) ? | 2667 |
| Clock multiplier ? | 20 |
| Package | 1156-land Flip-Chip Land Grid Array (FC-LGA8)
1.48" x 1.48" (3.75 cm x 3.75 cm) |
| Socket | Socket 1156 (LGA1156) |
| Weight | 0.9oz / 24.6g (CPU)
13.7oz / 388.6g (Box) |
| Fan/heatsink | E41759-002 |
| Introduction date | Sep 8, 2009 |
| Price at introduction | $196 |
| |
| Architecture / Microarchitecture |
| Processor core | Lynnfield |
| Core stepping | B1 (SLBLC) |
| Manufacturing process | 0.045 micron |
| Data width | 64 bit |
| Number of cores | 4 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 4 x 32 KB instruction caches
4 x 32 KB data caches |
| Level 2 cache size ? | 4 x 256 KB |
| Level 3 cache size | 8 MB shared cache |
| Features | - MMX instruction set
- SSE
- SSE2
- SSE3
- Supplemental SSE3
- SSE4.1 ?
- SSE4.2 ?
- EM64T technology ?
- Virtualization technology (VT-x)
- Execute Disable bit ?
- Turbo Boost technology ?
|
| Low power features | Enhanced SpeedStep technology ? |
| On-chip peripherals | - Integrated dual-channel DDR3 SDRAM Memory controller
- Direct Media Interface
- PCI-Express graphics
|
| |
| Electrical/Thermal parameters |
| Minimum/Maximum operating temperature (°C) ? | 5 - 72.7 |
| Maximum power dissipation (W) ? | 189.78 (peak)
160.08 (sustained) |
| Thermal Design Power (W) ? | 95 |
| |
| Notes on Intel BV80605001911AP |
- BXC80605I5750 is a Chinese version
- Memory controller supports DDR3-1066 and DDR3-1333 memory
- Direct Media Interface speed is 2.5 GT/s
|
CPU ID
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Core i5 i5-750 CPU.
| Manufacturer: | Intel |
| Family: | Core i5 |
| Processor Number: | i5-750 |
|
| Part number: | BV80605001911AP |
| S-Spec / Comment: | SLBLC |
| Submitted by: | CPU-World |
|
| General information |
|---|
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Core(TM) i5 CPU 750 @ 2.67GHz |
| Cores: | 4 |
| Logical processors: | 4 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 106E5 |
| Family: | 6 (06h) |
| Model: | 30 (01Eh) |
| Stepping: | 5 (05h) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB0: 2-MB or 4-MB pages, 4-way associative, 32 entries
Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Instruction TLB: 2-MB or 4-MB pages, fully associative, 7 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
L3 |
|---|
| Size: |
32 KB |
32 KB |
256 KB |
8 MB |
| Associativity: |
8-way set
associative |
4-way set
associative |
8-way set
associative |
16-way set
associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
64 bytes |
| |
| Instruction set extensions | Additonal instructions |
|---|
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| SSE4.1 |
MONITOR/MWAIT |
| SSE4.2 |
POPCNT |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
|---|
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| Intel Virtualization |
CPL qualified debug store |
| Intel Trusted Execution technology |
Debug store |
| Enhanced SpeedStep |
Debugging extensions |
| |
LAHF/SAHF support in 64-bit mode |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Model-specific registers |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Pending break enable |
| |
Perfmon and Debug capability |
| |
Physical address extensions |
| |
RDTSCP |
| |
Self-snoop |
| |
TSC rate is ensured to be invariant across all states |
| |
Thermal monitor |
| |
Thermal monitor and software controlled clock facilities |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
| |
xTPR Update Control |
