CPU ID
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Core i7 i7-860 CPU.
| Manufacturer: | Intel |
| Family: | Core i7 |
| Model / Processor Number: | i7-860 |
|
| Part number: | BV80605001908AK |
| S-Spec / Comment: | SLBJJ |
| Submitted by: | CPU-World |
|
| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Core(TM) i7 CPU 860 @ 2.80GHz |
| Cores: | 8 |
| Logical processors: | 16 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 106E5 |
| Family: | 6 (06h) |
| Model: | 30 (01Eh) |
| Stepping: | 5 (05h) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB0: 2-MB or 4-MB pages, 4-way associative, 32 entries
Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Instruction TLB: 2-MB or 4-MB pages, fully associative, 7 entries
Instruction TLB: 4-KB pages, 4-way set associative, 64 entries
Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries |
| Cache: |
L1 (data) |
L1 (instruction) |
L2 |
L3 |
| Size: |
32 KB |
32 KB |
256 KB |
8 MB |
| Associativity: |
8-way set associative |
4-way set associative |
8-way set associative |
16-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
64 bytes |
| |
| Instruction set extensions | Additonal instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| SSE4.1 |
MONITOR/MWAIT |
| SSE4.2 |
POPCNT |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| Hyper-Threading Technology |
CPL qualified debug store |
| Intel Virtualization |
Debug store |
| Intel Trusted Execution technology |
Debugging extensions |
| Enhanced SpeedStep |
LAHF/SAHF support in 64-bit mode |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Model-specific registers |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Pending break enable |
| |
Perfmon and Debug capability |
| |
Physical address extensions |
| |
RDTSCP |
| |
Self-snoop |
| |
TSC rate is ensured to be invariant across all states |
| |
Thermal monitor |
| |
Thermal monitor and software controlled clock facilities |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
| |
xTPR Update Control |