Specifications
| General information |
| Type | CPU / Microprocessor |
| Market segment | Desktop |
| Family | Intel Core i7 |
| Model number ? | i7-940 |
| CPU part numbers | AT80601000921AA is an OEM/tray microprocessor BX80601940 is a boxed processor (English version) BXC80601940 is a boxed processor (Chinese version) |
| Frequency ? | 2933 MHz |
| Turbo frequency | 3200 MHz (1 core)
3067 MHz (2 cores or more) |
| Bus speed ? | 2400 MHz QPI |
| Package | 1366-land Flip-Chip Land Grid Array (FC-LGA8) |
| Socket | Socket 1366 (LGA1366) |
| Weight | 1.2oz / 33.3g |
| Fan/heatsink | E29477-002 |
| Introduction date | Nov 17, 2008 |
| Price at introduction | $562 |
| |
| S-spec numbers |
| |
ES/QS processors |
Production processors |
| Part number |
Q1CS |
SLBCK |
| AT80601000921AA | + | + |
| BX80601940 | | + |
| BXC80601940 | | + |
|
| |
| Architecture / Microarchitecture |
| Microarchitecture | Nehalem (Nehalem) |
| Platform | X58 |
| Processor core ? | Bloomfield |
| Core stepping ? | C0 (SLBCK) |
| CPUID | 106A4 (SLBCK) |
| Manufacturing process | 0.045 micron Hi-k metal gate technology
731 million transistors |
| Die size | 263mm2 |
| Data width | 64 bit |
| The number of cores | 4 |
| The number of threads | 8 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 4 x 32 KB instruction caches
4 x 32 KB data caches |
| Level 2 cache size ? | 4 x 256 KB |
| Level 3 cache size | Inclusive shared 8 MB cache |
| Multiprocessing | Uniprocessor |
| Features | - MMX instruction set
- SSE
- SSE2
- SSE3
- Supplemental SSE3
- SSE4.1 ?
- SSE4.2 ?
- EM64T technology ?
- Hyper-Threading technology ?
- Turbo Boost technology ?
- Virtualization technology ?
- Execute Disable bit ?
|
| Low power features | - Thread C1, C3 and C6 states
- Core C1, C3 and C6 states
- Package C3 and C6 states
- Enhanced SpeedStep technology ?
|
| On-chip peripherals | - Integrated triple-channel DDR3 SDRAM Memory controller
- Quick Path Interconnect
|
| |
| Electrical/Thermal parameters |
| V core ? | 0.8V - 1.375V |
| Minimum/Maximum operating temperature ? | 5°C - 67.9°C |
| Minimum/Maximum power dissipation ? | 12 Watt (TDP in C6 state) / 230.14 Watt |
| Thermal Design Power ? | 130 Watt |
| |
| Notes on Intel AT80601000921AA |
- Memory controller supports DDR3-800 and DDR3-1066 memory
|
CPUs, related to Intel Core i7-940
• Highlighted numbers and features indicate whether specific processor performs better or worse than Core i7-940
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• Features abbreviations:
AES - AES instructions
TXT - Trusted Execution
Unlock - Unlocked multiplier
CPU ID (1)
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Core i7 I7-940 CPU.
| Manufacturer: | Intel |
| CPU Family: | Core i7 |
| Processor Number: | I7-940 |
| Frequency: | 2940 MHz |
|
| Part number: | AT80601000921AA |
| S-Spec Number: | SLBCK |
| Comment: | |
| Submitted by: | CPU-World |
|
| General information |
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Core(TM) i7 CPU 940 @ 2.93GHz |
| Cores: | 4 |
| Logical processors: | 8 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 106A4 |
| Family: | 6 (06h) |
| Model: | 26 (01Ah) |
| Stepping: | 4 (04h) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB0: 2-MB or 4-MB pages, 4-way associative, 32 entries
Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Instruction TLB: 2-MB or 4-MB pages, fully associative, 7 entries
Instruction TLB: 4-KB pages, 4-way set associative, 64 entries
Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
L3 |
| Size: |
32 KB |
32 KB |
256 KB |
8 MB |
| Associativity: |
8-way set associative |
4-way set associative |
8-way set associative |
16-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
64 bytes |
| |
| Instruction set extensions | Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| SSE4.1 |
MONITOR/MWAIT |
| SSE4.2 |
POPCNT |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| Hyper-Threading Technology |
Advanced programmable interrupt controller |
| Intel Virtualization |
CPL qualified debug store |
| Turbo Boost |
Debug store |
| Enhanced SpeedStep |
Debugging extensions |
| |
Digital Thermal Sensor capability |
| |
LAHF/SAHF support in 64-bit mode |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Model-specific registers |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Pending break enable |
| |
Perfmon and Debug capability |
| |
Physical address extensions |
| |
RDTSCP |
| |
Self-snoop |
| |
TSC rate is ensured to be invariant across all states |
| |
Thermal monitor |
| |
Thermal monitor 2 |
| |
Thermal monitor and software controlled clock facilities |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
| |
xTPR Update Control |