Specifications
| General information |
| Type | CPU / Microprocessor |
| Market segment | Desktop |
| Family | AMD Athlon II X2 |
| Model number ? | 240 |
| CPU part numbers | ADX240OCK23GQ is an OEM/tray microprocessor ADX240OCGQBOX is a boxed microprocessor |
| Stepping codes | CAEEC AE NAEIC AE |
| Frequency ? | 2800 MHz |
| Bus speed ? | 533 MHz Memory controller
One 2000 MHz 16-bit HyperTransport link |
| Clock multiplier ? | 14 |
| Package | 938-pin organic micro-PGA |
| Sockets | Socket AM2+ Socket AM3 |
| Fan/heatsink | AV-Z7LH01G101-2309 |
| Introduction date | July 22, 2009 |
| Price at introduction | $60 |
| |
| Architecture / Microarchitecture |
| Microarchitecture | K10 |
| Processor core ? | Regor |
| Core stepping ? | C2 |
| CPUID | 100F62 |
| Manufacturing process | 0.045 micron
234 million transistors |
| Die size | 117.5mm2 |
| Data width | 64 bit |
| The number of cores | 2 |
| The number of threads | 2 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 2 x 64 KB instruction caches
2 x 64 KB data caches |
| Level 2 cache size ? | 2 x 1 MB caches |
| Multiprocessing | Uniprocessor |
| Features | - MMX
- 3DNow!
- SSE
- SSE2
- SSE3
- SSE4A ?
- Advanced Bit Manipulation ?
- AMD64 technology ?
- AMD-V (virtualization) technology
- Enhanced Virus Protection ?
|
| Low power features | - Cool'n'Quiet 3.0
- CoolCore Technology ?
- Dual Dynamic Power Management ?
- Core C1 and C1E states
- Package S0, S1, S3, S4 and S5 states
|
| On-chip peripherals | - Integrated 144-bit DDR2/DDR3 Memory Controller
- HyperTransport 3 technology
|
| |
| Electrical/Thermal parameters |
| V core ? | 0.85V - 1.425V |
| Maximum operating temperature ? | 55°C - 74°C |
| Thermal Design Power ? | 65 Watt |
| |
| Notes on AMD ADX240OCK23GQ |
- The fastest supported memory is DDR2-1066 and DDR3-1066
|
CPUs, related to AMD Athlon II X2 240
• Highlighted numbers and features indicate whether specific processor performs better or worse than Athlon II X2 240
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• List of related CPUs is not complete.
• Features abbreviations:
Unlock - Unlocked multiplier
News
Sep 17, 2010: At the end of July we published preliminary specifications of Sempron
180 microprocessors. Recently, we acquired one the these Semprons, ran
a series of benchmarks on it, and compared them with test results of
other budget AMD and Intel CPUs. This mini-review presents partial
benchmarking results and our thoughts of them, and it will be useful
for those who consider buying either pre-built system with this
Sempron CPU, or OEM version of this microprocessor.
May 03, 2010: A few weeks ago we acquired a lot of Athlon II processors with C3 core revision. Although we posted pictures and individual benchmarks to Athlon II CPU pages, and added the results to our benchmark database more than a week ago, we decided to provide benchmarks in more readable format, i.e. as a review.
CPU ID (2)
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
AMD Athlon II X2 240 CPU.
| Manufacturer: | AMD |
| CPU Family: | Athlon II X2 |
| Model Number: | 240 |
| Frequency: | 2800 MHz |
|
| Part number: | ADX240OCK23GQ |
| Stepping Code: | CAEEC AE 0927FPMW |
| Comment: | |
| Submitted by: | CPU-World |
|
| General information |
| Vendor: | AuthenticAMD |
| Processor name (BIOS): | AMD Athlon(tm) II X2 240 Processor |
| Cores: | 2 |
| Logical processors: | 2 |
| Processor type: | Original OEM Processor |
| Core stepping: | DA-C2 |
| CPUID signature: | 100F62 |
| Family: | 16 (010h) |
| Model: | 6 (06h) |
| Stepping: | 2 (02h) |
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
2 x 64 KB |
2 x 64 KB |
2 x 1 MB |
| Associativity: |
2-way set associative |
2-way set associative |
16-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
| Lines per tag: |
1 |
1 |
1 |
| |
| Instruction set extensions | Additional instructions |
| MMX |
Advanced Bit manipulation |
| AMD extensions to MMX |
CLFLUSH |
| 3DNow! |
CMOV |
| Extensions to 3DNow! |
CMPXCHG16B |
| SSE |
CMPXCHG8B |
| SSE2 |
FXSAVE/FXRSTORE |
| SSE3 |
MONITOR/MWAIT |
| SSE4A |
POPCNT |
| |
PREFETCH/PREFETCHW |
| |
SYSCALL/SYSRET |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
| On-chip Floating Point Unit |
1 GB large page support |
| 64-bit / Intel 64 |
100MHz multiplier control |
| NX bit/XD-bit |
128-bit SSE instructions |
| Secure Virtual Machine (Virtualization) |
36-bit page-size extensions |
| PowerNow! / Cool'n'Quiet |
Advanced programmable interrupt controller |
| |
Core multi-processing legacy mode |
| |
Debugging extensions |
| |
Extended APIC space |
| |
Hardware P-state control |
| |
Hardware thermal control |
| |
Instruction based sampling |
| |
LAHF/SAHF support in 64-bit mode |
| |
LBR virtualization |
| |
LOCK MOV CR0 means MOV CR8 |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Misaligned SSE mode |
| |
Model-specific registers |
| |
Nested page tables |
| |
OS visible workaround |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Physical address extensions |
| |
RDTSCP |
| |
SKINIT and STGI support |
| |
SVM lock |
| |
Software thermal control |
| |
Support for NRIP save |
| |
THERMTRIP |
| |
TSC rate is ensured to be invariant across all states |
| |
Temperature sensor |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
| |
Watchdog timer support |
Our CPUID database has 2 records for this microprocessor. See all submitted records.