CPU Information
Athlon II X3 family was the last Athlon II family launched in 2009 - dual-core Athlon II CPUs were announced in June 2009, quad-core Athlon II processors were introduced in September, and triple-core X3 family was released in October. One of the first triple core Athlon II microprocessors was Athlon II X3 425. The 425 is based on Rana core, which is similar to quad-core Propus core with one core disabled. It is possible to unlock the disabled core on this and other Athlon II X3 processors on some socket AM3 motherboards by switching "Advanced Clock Calibration" BIOS option to "Auto". We unlocked the forth core on Athlon II 425 CPU, that we tested, but the unlocked core turned out to be defective. When the forth core was enabled, BIOS reported processor as "AMD Athlon(tm) II X4 B25 Processor". We could boot the system into DOS, which uses only one core. The system couldn't be booted into OS that supports all 4 processors. An attempt to unlock the forth core on our Athlon II X3 435 failed completely - with the forth core enabled, the system could not even pass BIOS Power-On Self Test.
| General information |
| Family | AMD Athlon II X3 |
| Model number ? | 425 |
| CPU part number | ADX425WFK32GI |
| Box part number | ADX425WFGIBOX |
| Stepping code | AADAC AD |
| Frequency (MHz) ? | 2700 |
| Bus speed (MHz) ? | - 667 MHz Memory controller
- One 2000 MHz 16-bit HyperTransport link
|
| Package | 938-pin organic micro-PGA |
| Sockets | Socket AM2+
Socket AM3 |
| Weight | 1.3oz / 37.6g |
| Introduction date | Oct 20, 2009 |
| Price at introduction | $76 |
| |
| Architecture / Microarchitecture |
| Processor core | Rana |
| Core stepping | C2 |
| Manufacturing process | 0.045 micron |
| Data width | 64 bit |
| Number of cores | 3 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 3 x 64 KB instruction caches
3 x 64 KB data caches |
| Level 2 cache size ? | 3 x 512 KB caches |
| Features | - MMX
- 3DNow!
- SSE
- SSE2
- SSE3
- SSE4a ?
- Advanced Bit Manipulation ?
- AMD64 technology ?
- AMD-V (virtualization) technology
- Enhanced Virus Protection ?
|
| Low power features | - Cool'n'Quiet 3.0
- CoolCore Technology ?
- Dual Dynamic Power Management ?
- Core C1 and C1E states
- Package S0, S1, S3, S4 and S5 states
|
| On-chip peripherals | - Integrated 144-bit DDR2 Memory Controller
- HyperTransport 3 technology
|
| |
| Electrical/Thermal parameters |
| Maximum operating temperature (°C) ? | 73 |
| Thermal Design Power (W) ? | 95 |
CPU ID
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
AMD Athlon II X3 425 CPU.
| Manufacturer: | AMD |
| Family: | Athlon II X3 |
| Model / Processor Number: | 425 |
|
| Part number: | ADX425WFK32GI |
| S-Spec / Comment: | AADAC AD0916APMW |
| Submitted by: | CPU-World |
|
| General information |
|---|
| Vendor: | AuthenticAMD |
| Processor name (BIOS): | AMD Athlon(tm) II X3 425 Processor |
| Cores: | 3 |
| Logical processors: | 3 |
| Processor type: | Original OEM Processor |
| Core stepping: | BL-C2 |
| CPUID signature: | 100F52 |
| Family: | 16 (010h) |
| Model: | 5 (05h) |
| Stepping: | 2 (02h) |
| Cache: |
L2 |
|---|
| Size: |
512 KB |
| Associativity: |
16-way set associative |
| Line size: |
64 bytes |
| Lines per tag: |
1 |
| |
| Instruction set extensions | Additonal instructions |
|---|
| MMX |
Advanced Bit manipulation |
| AMD extensions to MMX |
CLFLUSH |
| 3DNow! |
CMOV |
| Extensions to 3DNow! |
CMPXCHG16B |
| SSE |
CMPXCHG8B |
| SSE2 |
FXSAVE/FXRSTORE |
| SSE3 |
MONITOR/MWAIT |
| SSE4A |
POPCNT |
| |
PREFETCH/PREFETCHW |
| |
SYSCALL/SYSRET |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
|---|
| On-chip Floating Point Unit |
1 GB large page support |
| 64-bit / Intel 64 |
100MHz multiplier control |
| NX bit/XD-bit |
36-bit page-size extensions |
| Secure Virtual Machine (Virtualization) |
Advanced programmable interrupt controller |
| |
Core multi-processing legacy mode |
| |
Debugging extensions |
| |
Extended APIC space |
| |
Hardware P-state control |
| |
Hardware thermal control |
| |
Instruction based sampling |
| |
LAHF/SAHF support in 64-bit mode |
| |
LOCK MOV CR0 means MOV CR8 |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Misaligned SSE mode |
| |
Model-specific registers |
| |
OS visible workaround |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Physical address extensions |
| |
RDTSCP |
| |
SKINIT and STGI support |
| |
Software thermal control |
| |
THERMTRIP |
| |
TSC rate is ensured to be invariant across all states |
| |
Temperature sensor |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
| |
Watchdog timer support |
