CPU Information
Core revisions BA and B2, which correspond to part numbers ending with "BGC" and "BGD" respectively, had a Translation Look-aside Buffer (TLB) bug where, under certain conditions, the processor could lock up when loading cached TLB data. This bug was referenced in AMD documentation as errata 254: "Internal Resource Livelock Involving Cached TLB Reload". Temporary bug fix was to disable TLB caching, which had negative impact on processor performance. The temporary fix (or patch) was implemented in BIOS, and was also included into operating systems. On some motherboards it was possible to disable the patch in BIOS and thus increase performance by 10% on average. In cases, when disabling the patch was not supported by a motherboard, or when the patch was enabled by operating system regardless of the BIOS settings, it was still possible to disable the patch by manipulating MSR registers directly with the help of software tools.
| General information |
| Type | CPU / Microprocessor |
| Family | AMD Phenom X4 |
| Model number ? | 9500 |
| CPU part number | HD9500WCJ4BGD |
| Box part number | HD9500WCGDBOX |
| Stepping codes | AAAZB AA CAAAB AA CAAWB AA CAAZB AA JAAWB AA |
| Frequency (MHz) ? | 2200 |
| Bus speed (MHz) ? | - 533 MHz Memory controller
- One 1800 MHz 16-bit HyperTransport link
|
| Package | 940-pin organic micro-PGA |
| Sockets | Socket AM2
Socket AM2+ |
| Introduction date | Nov 19, 2007 |
| Price at introduction | $251 |
| |
| Architecture / Microarchitecture |
| Processor core | Agena |
| Core stepping | B2 |
| Manufacturing process | 0.065 micron SOI
450 million transistors |
| Die size | 285 mm2 |
| Data width | 64 bit |
| Number of cores | 4 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 4 x 64 KB 2-way associative instruction caches
4 x 64 KB 2-way associative data caches |
| Level 2 cache size ? | 4 x 512 KB 16-way set associative caches |
| Level 3 cache size | 2 MB 32-way set associative shared cache |
| Features | - MMX
- 3DNow!
- SSE
- SSE2
- SSE3
- SSE4a ?
- Advanced Bit Manipulation ?
- AMD64 technology ?
- AMD-V (virtualization) technology
- Enhanced Virus Protection ?
|
| Low power features | - Cool'n'Quiet 2.0
- CoolCore technology ?
- Independent Dynamic Core Technology ?
- Dual Dynamic Power Management ?
- Core C1 and C1E states
- Package S1, S3, S4 and S5 states
|
| On-chip peripherals | - Integrated dual-channel 144-bit DDR2 SDRAM Memory controller
- HyperTransport 3 technology
|
| |
| Electrical/Thermal parameters |
| V core (V) ? | 1.15 - 1.25 |
| V NorthBridge (V) | 1.25 |
| Maximum operating temperature (°C) ? | 55 - 70 |
| Thermal Design Power (W) ? | 95 |
| |
| Notes on AMD HD9500WCJ4BGD |
- On socket AM2+ platforms in the minimum performance state the processor runs at 1100 MHz / 1.05 Volt core voltage, and has TDP 66.1 Watt
- On socket AM2 platforms in the minimum performance state the processor runs at 1100 MHz / 1.15 - 1.25 Volt core voltage, and has TDP 67.2 Watt
|
CPU ID
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
AMD Phenom X4 9500 CPU.
| Manufacturer: | AMD |
| Family: | Phenom X4 |
| Model / Processor Number: | 9500 |
|
| Part number: | HD9500WCJ4BGD |
| S-Spec / Comment: | CAAZB AA 0748GPDW |
| Submitted by: | CPU-World |
|
| General information |
|---|
| Vendor: | AuthenticAMD |
| Processor name (BIOS): | AMD Phenom(tm) 9500 Quad-Core Processor |
| Cores: | 4 |
| Logical processors: | 4 |
| Processor type: | Original OEM Processor |
| Core stepping: | DR-B2 |
| CPUID signature: | 100F22 |
| Family: | 16 (010h) |
| Model: | 2 (02h) |
| Stepping: | 2 (02h) |
| Cache: |
L2 |
L3 |
|---|
| Size: |
512 KB |
2 MB |
| Associativity: |
16-way set associative |
32-way set associative |
| Line size: |
64 bytes |
64 bytes |
| Lines per tag: |
1 |
1 |
| |
| Instruction set extensions | Additonal instructions |
|---|
| MMX |
Advanced Bit manipulation |
| AMD extensions to MMX |
CLFLUSH |
| 3DNow! |
CMOV |
| Extensions to 3DNow! |
CMPXCHG16B |
| SSE |
CMPXCHG8B |
| SSE2 |
FXSAVE/FXRSTORE |
| SSE3 |
MONITOR/MWAIT |
| SSE4A |
POPCNT |
| |
PREFETCH/PREFETCHW |
| |
SYSCALL/SYSRET |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
|---|
| On-chip Floating Point Unit |
1 GB large page support |
| 64-bit / Intel 64 |
100MHz multiplier control |
| NX bit/XD-bit |
36-bit page-size extensions |
| Secure Virtual Machine (Virtualization) |
Advanced programmable interrupt controller |
| |
Core multi-processing legacy mode |
| |
Debugging extensions |
| |
Extended APIC space |
| |
Hardware P-state control |
| |
Hardware thermal control |
| |
Instruction based sampling |
| |
LAHF/SAHF support in 64-bit mode |
| |
LOCK MOV CR0 means MOV CR8 |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Misaligned SSE mode |
| |
Model-specific registers |
| |
OS visible workaround |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Physical address extensions |
| |
RDTSCP |
| |
Software thermal control |
| |
THERMTRIP |
| |
TSC rate is ensured to be invariant across all states |
| |
Temperature sensor |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
