Specifications
| General information |
| Type | CPU / Microprocessor |
| Market segment | Desktop |
| Family | AMD Phenom X4 |
| Model number ? | 9850 |
| CPU part numbers | HD985ZXAJ4BGH is an OEM/tray microprocessor HD985ZXAGHBOX is a boxed microprocessor |
| Stepping codes | JAAAB AA JAAFB AA JAAHB AA |
| Frequency ? | 2500 MHz |
| Bus speed ? | 533 MHz Memory controller
One 2000 MHz 16-bit HyperTransport link |
| Clock multiplier ? | 12.5 |
| Package | 940-pin organic micro-PGA |
| Sockets | Socket AM2 Socket AM2+ |
| Introduction date | Mar 27, 2008 |
| Price at introduction | $235 |
| |
| Architecture / Microarchitecture |
| Microarchitecture | K10 |
| Processor core ? | Agena |
| Core stepping ? | B3 |
| Manufacturing process | 0.065 micron SOI
450 million transistors |
| Die size | 285mm2 |
| Data width | 64 bit |
| The number of cores | 4 |
| The number of threads | 4 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 4 x 64 KB 2-way associative instruction caches
4 x 64 KB 2-way associative data caches |
| Level 2 cache size ? | 4 x 512 KB 16-way set associative caches |
| Level 3 cache size | 2 MB 32-way set associative shared cache |
| Multiprocessing | Uniprocessor |
| Features | - MMX
- 3DNow!
- SSE
- SSE2
- SSE3
- SSE4a ?
- Advanced Bit Manipulation ?
- AMD64 technology ?
- AMD-V (virtualization) technology
- Enhanced Virus Protection ?
|
| Low power features | - Cool'n'Quiet 2.0
- CoolCore technology ?
- Independent Dynamic Core Technology ?
- Dual Dynamic Power Management ?
- Core C1 and C1E states
- Package S1, S3, S4 and S5 states
|
| On-chip peripherals | - Integrated dual-channel 144-bit DDR2 SDRAM Memory controller
- HyperTransport 3 technology
|
| |
| Electrical/Thermal parameters |
| V core ? | 1.2V - 1.3V |
| V NorthBridge | 1.3V |
| Maximum operating temperature ? | 55°C - 61°C |
| Thermal Design Power ? | 125 Watt |
| |
| Notes on AMD HD985ZXAJ4BGH |
- The processor has unlocked multiplier
- On socket AM2+ platforms in the minimum performance state the processor runs at 1250 MHz / 1.05 Volt core voltage, and has TDP 69.7 Watt
- On socket AM2 platforms in the minimum performance state the processor runs at 1250 MHz / 1.2 - 1.3 Volt core voltage, and has TDP 89.4 Watt
|
CPUs, related to AMD Phenom X4 9850 (125W, BE)
• Highlighted numbers and features indicate whether specific processor performs better or worse than Phenom X4 9850 (125W, BE)
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• List of related CPUs is not complete.
• Features abbreviations:
Unlock - Unlocked multiplier
CPU ID (1)
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
AMD Phenom X4 9850 CPU.
| Manufacturer: | AMD |
| CPU Family: | Phenom X4 |
| Model Number: | 9850 |
| Frequency: | 2611 MHz |
|
| Part number: | HD985ZXAJ4BGH |
| Stepping Code: | |
| Comment: | |
| Submitted by: | |
|
| General information |
| Vendor: | AuthenticAMD |
| Processor name (BIOS): | AMD Phenom(tm) 9850 Quad-Core Processor |
| Cores: | 4 |
| Logical processors: | 4 |
| Processor type: | Original OEM Processor |
| Core stepping: | DR-B3 |
| CPUID signature: | 100F23 |
| Family: | 16 (010h) |
| Model: | 2 (02h) |
| Stepping: | 3 (03h) |
| Cache: |
L1 data |
L1 instruction |
L2 |
L3 |
| Size: |
4 x 64 KB |
4 x 64 KB |
4 x 512 KB |
2 MB |
| Associativity: |
2-way set associative |
2-way set associative |
16-way set associative |
32-way set associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
64 bytes |
| Lines per tag: |
1 |
1 |
1 |
1 |
| |
| Instruction set extensions | Additional instructions |
| MMX |
Advanced Bit manipulation |
| AMD extensions to MMX |
CLFLUSH |
| 3DNow! |
CMOV |
| Extensions to 3DNow! |
CMPXCHG16B |
| SSE |
CMPXCHG8B |
| SSE2 |
FXSAVE/FXRSTORE |
| SSE3 |
MONITOR/MWAIT |
| SSE4A |
POPCNT |
| |
PREFETCH/PREFETCHW |
| |
SYSCALL/SYSRET |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
| On-chip Floating Point Unit |
1 GB large page support |
| 64-bit / Intel 64 |
100MHz multiplier control |
| NX bit/XD-bit |
128-bit SSE instructions |
| Secure Virtual Machine (Virtualization) |
36-bit page-size extensions |
| PowerNow! / Cool'n'Quiet |
Advanced programmable interrupt controller |
| |
Core multi-processing legacy mode |
| |
Debugging extensions |
| |
Extended APIC space |
| |
Hardware P-state control |
| |
Hardware thermal control |
| |
Instruction based sampling |
| |
LAHF/SAHF support in 64-bit mode |
| |
LBR virtualization |
| |
LOCK MOV CR0 means MOV CR8 |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Misaligned SSE mode |
| |
Model-specific registers |
| |
Nested page tables |
| |
OS visible workaround |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Physical address extensions |
| |
RDTSCP |
| |
SVM lock |
| |
Software thermal control |
| |
Support for NRIP save |
| |
THERMTRIP |
| |
TSC rate is ensured to be invariant across all states |
| |
Temperature sensor |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |