AMD Phenom X4 microprocessor

Phenom X4 is the first quad-core microprocessor family based on K10 microarchitecture. First two members of Phenom X4 family, Phenom 9500 and 9600, were introduced in November 2007. Shortly after that AMD offered Black Edition of the Phenom 9600, and in a three more months, in March 2008, released remaining Phenom X4 microprocessors. At this time (March 2008) the lineup of Phenom quad-core microprocessors consists of 8 processors, including one mid-power CPU with model number 9100e, and two Black Edition CPUs.

All Phenom X4 processors include basic features of K10 micro-architecture:

  • Split 128 KB level 1 cache and exclusive 512 KB level 2 cache per core.
  • 2MB level 3 cache shared between all cores.
  • Support for Streaming SIMD Extensions up to SSE3.
  • SSE4a instructions.
  • AMD 64 technology.
  • Enhanced Virus Protection.
  • AMD-V virtualization technology.

The Phenom microprocessors support Cool'n'Quiet, CoolCore technology, and other power-saving features. Like other K8 and K10 families, the Phenoms use on-chip memory controller and one HyperTransport link to communicate with memory and peripheral devices. The HypertTransport link on almost all Phenom X4 CPUs is clocked at 1.8 GHz, which is almost twice as fast as the frequency of HyperTransport links in Third Generation Opterons.

Phenom X4 CPUs are manufactured in 940-pin micro-PGA package. The Phenom processors can be used in both socket AM2 and socket AM2+ motherboards. One of the main differences between these sockets is the version of supported HyperTransport protocol. Socket AM2 doesn't support newer and faster version of the HyperTransport protocol, like socket AM2+ does, as a result Phenom CPUs will automatically downgrade to slower HyperTransport protocol when they are plugged into socket AM2.

Phenom X4 CPUs use 4 digit model numbers that start from '9'. Remaining three digits in the model number indicate relative processor performance.

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K10 family
At a glance
Introduction:
Nov 19, 2007
Frequency (MHz):
1800 - 2500
Bus width:
64 bit
L2 cache size (KB):
512 (per core)
L3 cache size (KB):
2 MB
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