AMD Third Generation Opteron microprocessor family
The Third Generation Opterons are server-class processors that can work in two- and 8-way computer systems. Introduced on September 10, 2007, the Third Generation Opteron processors were the first quad-core microprocessors produced by AMD. Like all other CPUs based on the K10 microarchtecture, the Opterons have split 128 Kb level 1 cache and exclusive 512 KB level 2 cache per core. The CPUs also include large level 3 cache shared between all four cores. The Opteron CPUs support all streaming SIMD extensions up to SSE3, and include 4 new SSE4a instructions. The Opterons feature AMD64 technology, AMD-V virtualization technology, Enhanced Virus Protection or NX-bit, and incorporate many power saving features. Like K8 microprocessors, the Third Generation Opterons don't use Front-Side Bus. Instead, the processors use on-chip memory controller to talk directly to DDR2 SDRAM memory, and three high-speed HyperTransport links to communicate with peripheral devices and other microprocessors in multi-processing system.
On November 13, 2008, AMD released 45 micron version of the Third Generation Opteron processors, codenamed "Shanghai". New Opteron processors feature larger L3 cache with lower latency, HyperTransport 3.0 protocol, support for DDR2-800 memory and enhanced memory pre-fetching. Also new in these processors is a power-saving feature called "Smart Fetch" which allows the CPU to reduce power consumption by loading idle core's L1 and L2 cache data into L3 cache, and then switching the core to "halt" state. New processors with "Shanghai" core are manufactured in the same package as 65-micron "Barcelona" processors, and work in socket F(1207) motherboards.
Model numbers of Third Generation Opteron CPUs are similar to model numbers of Second Generation Opterons. Opteron model numbers consist of 4 digits:
Low-power Opteron processors have model numbers with 'HE' suffix.
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At a glance
Sep 10, 2007
The number of cores:
1.7 - 3.1
L3 cache size (MB):