AMD K6-2 processor families

Released in 1998, the AMD K6-2 microprocessor is an evolutionary update to AMD K6 processor. The K6-2 is based on the same RISC86 core as the K6. This core does not directly execute x86 instructions. Instead, it translates each x86 instruction into one or more simpler fixed-length RISC86 instructions that are stored in scheduler buffer. Each clock cycle the scheduler can issue up to 6 RISC86 instructions to the following 10 executions units: two integer units, two MMX units, load, store, floating-point, branch condition, and 3DNow! ALU multiplier units. The units are independent of each other, and can execute RISC86 instructions concurrently. While the RISC86 instructions can be executed out-of-order by the K6-2 core, the scheduler unit retires instructions in order. Up to 4 RISC86 instructions can be retired per clock cycle.

As already been mentioned, the K6-2 has 10 execution units, i.e. it has 3 more execution units than its predecessor AMD K6. Two extra execution units are used to support 3DNow! - these Single Instruction Multiple Data (SIMD) instructions are somewhat similar to MMX instructions except that 3DNow! works with single-precision floating-point numbers, while MMX works only with integer numbers. Using 3DNow! for floating-point calculations could significantly boost performance of FPU intensive applications that didn't require high floating-point precision (for example, games). Another extra K6-2 execution unit was second MMX ALU unit. Adding second MMX unit to the CPU significantly improved performance of MMX operations.

Many AMD K6-2 processors supported 100 MHz bus speed. Increasing bus speed of K6-2 processors by 50% (from 66 MHz to 100 MHz) while keeping CPU frequency the same resulted in additional 10% performance boost.