| General information |
| Type | CPU / Microprocessor |
| Family | AMD Turion 64 X2 Mobile technology |
| Model number ? | TL-50 |
| Part number | TMDTL50HAX4CT |
| Stepping codes | ADB5F CDB5F LDB5F LDB8F |
| Frequency (MHz) ? | 1600 |
| Package | 638-pin lidless micro-PGA
1.38" x 1.38" (3.5 cm x 3.5 cm) |
| Socket | Socket S1 |
| Introduction date | May 17, 2006 |
| Price at introduction | $184 |
| |
| Architecture / Microarchitecture |
| Manufacturing process | 0.09 micron SOI |
| Data width | 64 bit |
| Number of cores | 2 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 2 x 64 KB 2-way associative instruction cache
2 x 64 KB 2-way associative data cache |
| Level 2 cache size ? | 2 x 256 KB 16-way associative exclusive cache |
| Physical memory | 1 TB |
| Virtual memory (TB) | 256 |
| Features | - MMX technology
- SSE
- SSE2
- SSE3
- AMD64 technology ?
- Virtualization technology
- Enhanced Virus Protection ?
|
| Low power features | - Power Now!
- Deeper Sleep state
|
| On-chip peripherals | - Dual-channel DDR2 SDRAM memory controller
- One 16-bit HyperTransport link with speeds up to 800 MHz
|
| |
| Electrical/Thermal parameters |
| V core (V) ? | 1.075 / 1.1 |
| Max operating temperature (°C) ? | 95 |
| Thermal Design Power (W) ? | 31 |
| |
| Notes on AMD TMDTL50HAX4CT |
- TMDTL50HAX4CT is an OEM/tray processor
- TMDTL50CTWOF is a boxed processor
- Core revision F2
|
AMD Turion 64 X2 Mobile technology TL-50 - TMDTL50HAX4CT
pic of TMDTL50HAX4CT