NXP LPC1100 microcontroller family
NXP LPC1100 is a family of ultra low-power microcontrollers based on ARM Cortex-M0 core. NXP Semiconductors licensed the Cortex-M0 design at the same day as the design was officially announced by ARM, on February 23, 2009. The LPC 1100 family was launched 9 months later, in November 2009. ARM Cortex-M0 core uses a superset of Thumb instruction set, and adds a few Thumb-2 system instructions. Despite the fact that the core is 32-bit, all instructions are 16-bit wide, which results in very compact code. In addition to the Cortex-M0 RISC core, the LPC1100 microcontrollers include from 8 KB to 32 KB of Flash programmable memory, from 2 KB to 8 KB of SRAM, and the following peripherals: UART, one or two SPI controllers, I2 bus interface, clock oscillator, 8-channel 10-bit ADC, four general purpose timers/counters and a system timer.
LPC 1100 family supports three low-power modes - Sleep, Deep-sleep and Deep power-down mode. Sleep mode reduces power consumption by more than 75% by stopping the CPU core clock. Deep-sleep mode does not only stop the CPU core clock, but also turns off power to analog blocks. User program can chose which analog blocks can be turned off or left on in the deep-sleep mode. The lowest possible power saving mode, Deep power-down, turns off the power for the whole chip.
The LPC1100 microcontrollers are produced in three different package types, with the smallest package size being 7mm x 7mm. New member of the LPC110 family, LPC1102, which at this time (April 2010) is sampled, is going to have significantly smaller package size - 2.17 mm x 2.32 mm x 0.6 mm.