Rise Technology MP6 family

CPU » Rise Technology » MP6 family

Rise MP6 is a superpipelined and superscalar microprocessor designed as a low-cost and low-power alternative to Intel Pentium MMX family. The MP6 processor is fully compatible with x86 instruction set, supports MMX instructions, and runs at Front Side Bus frequencies up to 100 MHz and processor core frequencies up to 250 MHz. The processor has three integer units and three MMX pipelines which allows the CPU to execute up to three integer or MMX instructions in a single cycle. Fully pipelined floating point unit can execute up to two floating-point instructions per cycle. To improve processor performance the core utilizes branch prediction and a number of techniques used to resolve data dependency conflicts. Superpipelined architecture, multiple integer units and other core performance-enhancement features result in an equal or better integer, MMX and floating-point performance of the MP6 processors when compared to similar clocked AMD K6 and Intel Pentium MMX CPUs. Regrettably, all MP6 microprocessors, with the exception of the lowest clocked 166 MHz CPU, use "PR" rating, which is 22% - 46% higher than processor's internal frequency. This results in slower or significantly slower MP6 CPU performance when compared to AMD K6 and Intel Pentium MMX/Pentium II CPUs microprocessors running at MP6 rated frequency.

The Rise MP6 processors are manufactured in small 387-ball BGA package. Desktop versions of the processor are manufactured in the same package mounted on a Socket 7 PGA adapter.

Information below was provided to us by Chris Norrie:

Here's an interesting tidbit. If you put ascii "NZ" into eAX and execute CPUID it will return "* Chris Norrie *" in eAX through eDX. This easter egg is designed into the hardware. Easter eggs are common in software but not so common in hardware.

I know this because I designed it. I am from New Zealand, hence the NZ in eAX.

The tricky part was getting to tapeout without the easter egg being caught and removed. One of our tests was to ensure all microcode locations had been executed during verification. So I fanagled writing some of the critical verification tests myself and hiding the necessary code to exercise all paths in CPUID. What made life more difficult was the fact I had used all 640 microcode locations (including my easter egg). So we had no wiggle room left. There were times I had to be quite creative in order to keep the easter egg. Fortunately, since I was a principal engineer and there were only a handful of designers, I had enough clout to be responsible for the necessary parts of the design to pull all this off without arousing suspicion.

It was quite something to write a few lines of assembly to do a CPUID, save the registers to memory and call the BIOS to print the string to the screen. One of my more proud moments!