Cyrix MXi microprocessor family

Details about MXi highly integrated processor were announced by Cyrix Corporation in the second half of 1997. The MXi microprocessor was supposed to integrate large number of peripherals on the chip including:

• Low-latency 128-bit DDR SDRAM controller with memory bandwidth greater than 2GB per second.
• 66 MHz PCI controller.
• Faster than 4x AGP controller.
• Direct3D compliant 2D graphics accelerator with support of screen resolutions up to 1600 x 1200.
• MPEG2/DVD accelerator.
• Direct3D and OpenGL compliant 3D accelerator with fill rate greater than 120 million pixels per second, and rendering speed greater than 2 million triangles per second.

The microprocessor was based on newly announced Cayenne core. The core featured enhanced integer unit and dual-issue fully pipelined MMX and floating point unit. MMX unit included 15 new multimedia instructions. The MXi was planned to be released in the second half of 1998 with minimum rated speed 300 MHz.