VIA Nano microprocessor family
VIA Nano is a family of low- and ultra-low power single-core microprocessors, that succeeded VIA C7 family. Nano CPUs are built on Isaiah microarchitecture - a superscalar and speculative out-of-order architecture, that employs newer 65nm manufacturing process. The processors incorporate a single CPU core with two-level cache hierarchy. Nano's instruction and data level 1 caches have the same 64 KB size, but greater associativity than C7 counterparts. Level 2 cache on Nano chips was increased to 1 MB. The microprocessors support SIMD instructions up to SSE4.1 (Supplemental SSE3 on 1000/2000 series), and they also add support for x86-64 extensions to the instruction set. Another new feature on Nano chips is Virtualization technology, however it was only available on newer processors. All products from Nano family integrate Padlock Security Engine, which accelerates AES encryption, provides secure hash algorithms, and generates unpredictable random numbers. The Padlock engine also supports NX bit feature, that stops certain types of viruses by marking data memory pages as non-executable.
In addition to out-of-order architecture, larger L2 cache and new technologies, Isaiah processors include numerous performance enhancements, such as:
VIA Nano CPUs support the same lower power states as C7 parts. On top of that, they add a new C6 state, that turns off processor caches after flushing them and saving their state. Nano microprocessors also include Adaptive PowerSaver feature, that operates similar to AMD PowerNow! and Intel's SpeedStep technologies. The PowerSaver technology can throttle down clock frequency and voltage to save power, and restore it to default values when maximum performance is required. These operations can be done in a single cycle on Nano processors. Another feature, called Adaptive Thermal Limit, is used to set the maximum operating temperature, that shouldn't be exceeded.
VIA Nano CPUs are manufactured in a nanoBGA package, and they are fully pin-compatible with C7 microprocessors and older chipsets.
At a glance
0.8 - 2
L2 cache size (MB):
3.5 - 25