VIA Nano microprocessor family

VIA Nano is a family of low- and ultra-low power single-core microprocessors, that succeeded VIA C7 family. Nano CPUs are built on Isaiah microarchitecture - a superscalar and speculative out-of-order architecture, that employs newer 65nm manufacturing process. The processors incorporate a single CPU core with two-level cache hierarchy. Nano's instruction and data level 1 caches have the same 64 KB size, but greater associativity than C7 counterparts. Level 2 cache on Nano chips was increased to 1 MB. The microprocessors support SIMD instructions up to SSE4.1 (Supplemental SSE3 on 1000/2000 series), and they also add support for x86-64 extensions to the instruction set. Another new feature on Nano chips is Virtualization technology, however it was only available on newer processors. All products from Nano family integrate Padlock Security Engine, which accelerates AES encryption, provides secure hash algorithms, and generates unpredictable random numbers. The Padlock engine also supports NX bit feature, that stops certain types of viruses by marking data memory pages as non-executable.

In addition to out-of-order architecture, larger L2 cache and new technologies, Isaiah processors include numerous performance enhancements, such as:

  • Multiple data prefetch mechanisms, that load pre-fetched data directly into L1 or L2 caches, or into a special small pre-fetch cache
  • Macro-fusion feature, that can merge certain combinations of x86 instructions into a single micro-op (internal instruction).
  • Micro-fusion feature can merge two or more micro-ops into a single micro-op.
  • Advanced Branch prediction, that uses 8 different predictors with different algorithms to guess branch results.
  • SSE unit with 128-bit wide execution path. The unit requires only one cycle to execute most SSE integer instructions.
  • Turbo feature, that increases CPU clock rate above nominal, and keeps the processor "overclocked" as long as it stays within thermal limits. This features was implemented only on some SKUs.
  • Ability to decode 3 x86 instructions, issue 7 micro-ops, and retire 3 fused micro-ops per cycle.

VIA Nano CPUs support the same lower power states as C7 parts. On top of that, they add a new C6 state, that turns off processor caches after flushing them and saving their state. Nano microprocessors also include Adaptive PowerSaver feature, that operates similar to AMD PowerNow! and Intel's SpeedStep technologies. The PowerSaver technology can throttle down clock frequency and voltage to save power, and restore it to default values when maximum performance is required. These operations can be done in a single cycle on Nano processors. Another feature, called Adaptive Thermal Limit, is used to set the maximum operating temperature, that shouldn't be exceeded.

VIA Nano CPUs are manufactured in a nanoBGA package, and they are fully pin-compatible with C7 microprocessors and older chipsets.

Use the filter below to display families that have specific feature(s) incorporated:
Embedded Mobile
SSE4 Virtualization

List of Nano families

Nano 3000 series was announced in November, 2009. Like 1000/2000 series, these processors were built on 65nm technology, but their design was optimized, resulting in about 20% better performance at up to 20% lower power consumption at the same frequency (the numbers are according to VIA). The 3000 series also added SSE4 instructions, and supported Virtualization technology. The series was comprised of several low- and ultra-low power SKUs, with frequencies ranging from 1 GHz to 2 GHz. The CPUs were produced in NanoBGA2 package, and they were pin-compatible with older 1000/2000 series parts.
Nano E-Series was a marketing name for embedded Nano microprocessors. These CPUs were based on the same technology, and supported same features as 1000, 2000 and 3000 series consumer-oriented chips.
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At a glance

64-bit microprocessor
May 2008
Technology (micron):
Frequency (GHz):
0.8 - 2
L2 cache size (MB):
TDP (Watt):
3.5 - 25