VIA Nano X2 microprocessor family
VIA Nano X2 family of ultra-low power microprocessors was announced in January 2011, and embedded versions of these processors, dubbed Nano X2 E-Series, were introduced three months later. Compared to their predecessors, the main new feature of X2 CPUs was addition of the second core, which significantly improved performance of multi-threaded applications. VIA also switched to more modern 40nm manufacturing process, that allowed them to fit both cores on a die, only a few percent larger than the die of single-core Nano CPUs. Many Nano X2 processors also had Front Side Bus frequency raised to 1066 MHz, however remaining processor features stayed unchanged from Nano 3000 series.
The Nano X2 processor is implemented as two "Isaiah" cores, each with their own L1 and L2 caches, on a single die. The "Isaiah" is a superscalar out-of-order microarchitecture, which is able to decode and retire three x86 instructions per cycle. Internally the processor converts all x86 instructions into micro-ops, which are then queued for one of the following execution units: ALU1 and ALU2, store address and data ports, media-A and media-B units, and load port. Executed micro-ops are retired in the program order. To improve efficiency, the CPU employs macro-fusion feature, that can combine multiple x86 instructions into a single micro-op, and a micro-fusion feature, that combines multiple micro-ops into one. The microarchitecture also makes use of other modern techniques, like advanced branch prediction and data pre-fetching into L1 or L2 cache, to improve CPU performance.
Nano X2 microprocessors have two-level cache architecture. Each CPU core comes with dedicated 64 KB data and 64 KB instruction level 1 caches, and 1 MB level 2 cache. The cores support several extensions to x86 instruction set, including 64-bit instructions, MMX, and SIMD instructions up to SSE 4.1. The processors also incorporate such technologies as Execute disable bit, sometimes called NX or XD bit, and Virtualization. All Nano X2 chips include Padlock Security Engine, which is used to accelerate AES encryption, generate unpredictable random numbers, and provide secure hash algorithm. Some Nano X2 parts also support Turbo technology. That feature can increase CPU performance by raising operating frequency above nominal, and keep it that way as long as the part performs within thermal limits.
VIA Nano X2 processors do not have integrated memory controller, and they utilize Front Side Bus interface to communicate with memory and peripheral components. The FSB is clocked at 200 or 266 MHz. Because the bus transmits data 4 times per clock, this results in 800 MHz or 1066 MHz effective bus frequency.
Nano X2 microprocessors support a few lower power states, that reduce power consumption when the cores are idle. To lower power in active state, the CPUs use Enhanced PowerSaver feature. Under light loads, that technology throttles clock frequency and voltage down, thus saving the power, and restores them back to default values when maximum performance is needed.
VIA Nano X2 CPUs are manufactured in a nanoBGA package, and they are fully pin-compatible with Nano and C7 microprocessors.
At a glance
Jan 4, 2011
The number of cores:
1.2 - 1.6
L2 cache size (MB):