Intel Pentium Pro 180 256 KB - KB80521EX180 256K (BP80521180 256K)

CPU Information

General information
TypeCPU / Microprocessor
FamilyIntel Pentium Pro
CPU part numberKB80521EX180 256K (Q033, Q035, Q0871, Q0907, SL22S, SL22U, SY012, SY031, SY039)
Box part numberBP80521180 256K (SL23L, SU103)
Frequency (MHz)  ? 180
Bus speed (MHz)  ? 60
Clock multiplier  ? 3
Package387-pin Modified Staggered Ceramic Pin Grid Array with gold plated heat spreader
2.66" x 2.46" (6.76 cm x 6.25 cm)
SocketSocket 8
Introduction date1-Nov-95
Upgrade optionsPentium II Overdrive
 
Architecture / Microarchitecture
Core steppingssA0 (SY012)
sA1 (Q0871, Q0907, SU103, SY031, SY039)
sB1 (Q033, Q035, SL22S, SL22U, SL23L)
Manufacturing process0.35 and 0.6 micron
5.5 million transistors
Data width32 bit
Data bus width64 bit
Floating Point UnitIntegrated
Level 1 cache size  ? 8 KB four-way set associative code
8 KB two-way set associative data
Level 2 cache size  ? 256 KB
 
Electrical/Thermal parameters
V core (V)  ? 3.3
Minimum/Maximum operating temperature (°C)  ? 0 - 85
Minimum/Typical/Maximum power dissipation (W)0.3 / 24.8 / 31.7

Pictures (2)

Intel Pentium Pro 180 256 KB - KB80521EX180 256K (BP80521180 256K)

180 MHz
256 KB L2 cache
387-pin modified SPGA
Gold plated heat spreader

Image reduced 2x times
Intel Pentium Pro 180 256 KB - KB80521EX180 256K (BP80521180 256K)
 
2008-09-25 12:02:34
Posted by: Zdenek

 
 

CPU ID

NOTE: CPU ID information below was taken from one CPU and may include features that are not present in all different steppings of the Intel Pentium Pro 180 MHz CPU.

Manufacturer:Intel
Family:Pentium Pro
Model / Processor Number:180 MHz
Part number:KB80521EX180 256K
S-Spec / Comment:SY031
Submitted by:cocoe
General information
Vendor:GenuineIntel
Processor type:Original OEM Processor
CPUID signature:617
Family: 6 (06h)
Model: 1 (01h)
Stepping: 7 (07h)
TLB/Cache details:Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Data TLB: 4-MB Pages, 4-way set associative, 8 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 32 entries
Instruction TLB: 4-MB Pages, fully associative, 2 entries

Cache: L1 (data) L1 (instruction) L2
Size: 8 KB 8 KB 256 KB
Associativity: 2-way set associative 4-way set associative 4-way set associative
Line size: 32 bytes 32 bytes 32 bytes
 
Instruction set extensionsAdditonal instructions
  CMOV
  CMPXCHG8B
 
Major featuresOther features
On-chip Floating Point Unit Debugging extensions
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page global extension
  Page-size extensions (4MB pages)
  Physical address extensions
  Time stamp counter
  Virtual 8086-mode enhancements

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