Intel Mobile Pentium III 450 - KP80526NY450256 (BXM80526B450256)

CPU Information

General information
TypeCPU / Microprocessor
FamilyIntel Mobile Pentium III
CPU part numberKP80526NY450256 (QE30, SL3LG, SL43N, SL4JQ)
Box part numberBXM80526B450256 (SL3RF)
Frequency (MHz)  ? 450
Bus speed (MHz)  ? 100
Clock multiplier  ? 4.5
Package495-pin micro-PGA2 (PPGA-B495)
1.35" x 1.11" (3.42 cm x 2.83 cm)
Introduction dateOct 25, 1999
Price at introduction$348
 
Architecture / Microarchitecture
Processor coreCoppermine
Core steppingsPA2 (SL3LG, SL3RF)
PB0 (SL43N)
PC0 (SL4JQ)
Manufacturing process0.18 micron
28 million transistors
Data width32 bit
Floating Point UnitIntegrated
Level 1 cache size  ? 16 KB 4-way set associative instruction cache
16 KB 4-way set associative write-back data cache
Level 2 cache size  ? 256 KB 8-way set associative on-die cache
Features
  • MMX technology
  • SSE
Low power features
  • Stop Grant mode  ? 
  • Auto Halt mode  ? 
  • Sleep mode  ? 
  • Deep Sleep mode  ? 
  • Quick Start mode
 
Electrical/Thermal parameters
Min/Recommended/Max V core (V)1.485 / 1.6 / 1.64
Minimum/Maximum operating temperature (°C)  ? 0 - 100
Minimum/Maximum power dissipation (W)  ? 2.12 (Stop Grant mode) / 15.74
 
Notes on Intel KP80526NY450256
  • Markings on the processor are "KP 450/256"

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CPU ID

NOTE: CPU ID information below was taken from one CPU and may include features that are not present in all different steppings of the Intel Mobile Pentium III 450 MHz / 495 pin CPU.

Manufacturer:Intel
Family:Mobile Pentium III
Model / Processor Number:450 MHz / 495 pin
Part number:KP80526NY450256
S-Spec / Comment:SL3LG
Submitted by:cocoe
General information
Vendor:GenuineIntel
Processor type:Original OEM Processor
CPUID signature:681
Family: 6 (06h)
Model: 8 (08h)
Stepping: 1 (01h)
TLB/Cache details:Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Data TLB: 4-MB Pages, 4-way set associative, 8 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 32 entries
Instruction TLB: 4-MB Pages, fully associative, 2 entries

Cache: L1 (data) L1 (instruction) L2
Size: 16 KB 16 KB 256 KB
Associativity: 4-way set associative 4-way set associative 8-way set associative
Line size: 32 bytes 32 bytes 32 bytes
 
Instruction set extensionsAdditonal instructions
MMX CMOV
SSE CMPXCHG8B
  FXSAVE/FXRSTORE
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
  Debugging extensions
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Physical address extensions
  Time stamp counter
  Virtual 8086-mode enhancements

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