Specifications
| General information |
| Type | CPU / Microprocessor |
| Market segment | Desktop |
| Family | Intel Pentium III |
| Model number ? | 500E |
| CPU part numbers | RB80526PY500256 is an OEM/tray microprocessor BX80526F500256 is a boxed microprocessor BX80526F500256E is a boxed microprocessor |
| Frequency ? | 500 MHz |
| Bus speed ? | 100 MHz |
| Clock multiplier ? | 5 |
| Package | 370-pin Flip-Chip Pin Grid Array (FC-PGA)
1.95" x 1.95" (4.95 cm x 4.95 cm) |
| Socket | Socket 370 |
| Introduction date | Oct 25, 1999 |
| Price at introduction | $239 |
| |
| S-spec numbers |
| |
Production processors |
| Part number |
SL3Q9 |
SL3R2 |
SL446 |
SL45R |
| BX80526F500256 | | + | + | + |
| BX80526F500256E | | + | | |
| RB80526PY500256 | + | + | + | |
|
| |
| Architecture / Microarchitecture |
| Microarchitecture | P6 |
| Processor core ? | Coppermine |
| Core steppings ? | cA2 (SL3Q9, SL3R2) cB0 (SL446, SL45R) |
| CPUIDs | 681 (SL3Q9, SL3R2) 683 (SL446, SL45R) |
| Manufacturing process | 0.18 micron
28 million transistors |
| Data width | 32 bit |
| Data bus width | 64 bit |
| The number of cores | 1 |
| The number of threads | 1 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 16 KB instruction cache
16 KB data cache |
| Level 2 cache size ? | Full-speed integrated 8-way set associative 256 KB |
| Features | - MMX technology
- SSE instructions
|
| Low power features | - AutoHALT state ?
- Stop Grant state ?
- Sleep state ?
- Deep Sleep state ?
- System Management Mode
|
| |
| Electrical/Thermal parameters |
| Min/Recommended/Max V core | 1.52V / 1.6V / 1.64V |
| Minimum/Maximum operating temperature ? | 0°C - 85°C |
| Maximum power dissipation ? | 16 Watt |
| |
| Notes on Intel RB80526PY500256 |
- The processor can be marked as 500E/256/100/1.6V
|
CPUs, related to Intel Pentium III 500E (Socket 370)
• Within each category, the CPUs are sorted from slower (at the top) to faster (at the bottom)
• List of related CPUs is not complete.
CPU ID (1)
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Pentium 3 500 CPU.
| Manufacturer: | Intel |
| CPU Family: | Pentium 3 |
| Processor Number: | 500 |
| Frequency: | 501 MHz |
|
| Part number: | RB80526PY500256 |
| S-Spec Number: | SL3Q9 |
| Comment: | |
| Submitted by: | Neon |
|
| General information |
| Vendor: | GenuineIntel |
| Processor type: | Original OEM Processor |
| CPUID signature: | 681 |
| Family: | 6 (06h) |
| Model: | 8 (08h) |
| Stepping: | 1 (01h) |
| TLB/Cache details: | Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Data TLB: 4-MB Pages, 4-way set associative, 8 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 32 entries
Instruction TLB: 4-MB Pages, fully associative, 2 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
16 KB |
16 KB |
256 KB |
| Associativity: |
4-way set associative |
4-way set associative |
8-way set associative |
| Line size: |
32 bytes |
32 bytes |
32 bytes |
| |
| Instruction set extensions | Additional instructions |
| MMX |
CMOV |
| SSE |
CMPXCHG8B |
| |
FXSAVE/FXRSTORE |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| |
Debugging extensions |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Model-specific registers |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Physical address extensions |
| |
Processor serial number |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |