Intel Mobile Pentium 4 2.4 GHz - RK80532GE056512

CPU Information

General information
TypeCPU / Microprocessor
FamilyIntel Mobile Pentium 4
CPU part numberRK80532GE056512 (QWS2, SL723)
Frequency (MHz)  ? 2400
Bus speed (MHz)  ? 533
Clock multiplier  ? 18
Package478-pin Flip-Chip Pin Grid Array (FC-PGA2)
1.38“ x 1.38“ (3.5 cm x 3.5 cm)
SocketSocket 478 (mPGA478B)
Introduction dateJun 11, 2003
 
Architecture / Microarchitecture
Processor coreNorthwood
Core steppingD1 (SL723)
Manufacturing process0.13 micron
55 million transistors
Data width32 bit
Floating Point UnitIntegrated
Level 1 cache size  ? Execution trace cache for up to 12K decoded micro-operations
Level 2 cache size  ? 512 KB
Features
  • MMX technology
  • SSE
  • SSE2
  • Thermal Monitor
Low power features
  • SpeedStep technology  ? 
  • Auto-Halt mode  ? 
  • Stop Grant mode  ? 
  • Sleep mode  ? 
  • Deep Sleep mode  ? 
  • Deeper Sleep mode  ? 
  • Address bus powerdown
 
Electrical/Thermal parameters
V core (V)  ? 1.475 - 1.525
Minimum/Maximum operating temperature (°C)  ? 5 - 71
Minimum/Maximum power dissipation (W)  ? 69.97 (1.475V)
71.23 (1.5V)
34.06 (Stop Grant mode) / 72.5 (1.525V)
Thermal Design Power (W)  ? 59.8
 
Notes on Intel RK80532GE056512
  • Bus frequency is 133 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 533 MHz
  • Processor frequency is reduced to 1.6 GHz in battery-optimized mode (1.2V)
  • Maximum power dissipation in battery-optimized mode is 38.87W

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CPU ID

NOTE: CPU ID information below was taken from one CPU and may include features that are not present in all different steppings of the Intel Mobile Intel Pentium 4 2.40 GHz CPU.

Manufacturer:Intel
Family:Mobile Intel Pentium 4
Model / Processor Number:2.40 GHz
Part number:RK80532GE056512
S-Spec / Comment:SL723
Submitted by:cocoe
General information
Vendor:GenuineIntel
Processor name (BIOS): Mobile Intel(R) Pentium(R) 4 CPU 2.40GHz
Logical processors:1
Processor type:Original OEM Processor
CPUID signature:F29
Family:15 (0Fh)
Model: 2 (02h)
Stepping: 9 (09h)
TLB/Cache details:Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries
Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries
No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache

Cache: L1 (data) L1 (instruction) L2
Size: 8 KB 12K uops 512 KB
Associativity: 4-way set associative 8-way set associative 8-way set associative
Line size: 64 bytes   64 bytes
Other: sectored cache   sectored cache
 
Instruction set extensionsAdditonal instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG8B
  FXSAVE/FXRSTORE
  SYSENTER/SYSEXIT
 
Major featuresOther features
On-chip Floating Point Unit 36-bit page-size extensions
  Advanced programmable interrupt controller
  Debug store
  Debugging extensions
  L1 context ID
  Machine check architecture
  Machine check exception
  Memory-type range registers
  Model-specific registers
  Page attribute table
  Page global extension
  Page-size extensions (4MB pages)
  Pending break enable
  Physical address extensions
  Self-snoop
  Thermal monitor
  Thermal monitor and software controlled clock facilities
  Time stamp counter
  Virtual 8086-mode enhancements
  xTPR Update Control

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