Intel Pentium 4 2.8 GHz - RK80532PG072512 (BX80532PG2800D)
Specifications
| General information | |
| Type | CPU / Microprocessor |
| Market segment | Desktop |
| Family | Intel Pentium 4 |
| CPU part number | RK80532PG072512 (QWA5, QWK5, QWP6ES, SL6WJ, SL6WT, SL78Y) |
| Box part number | BX80532PG2800D (SL6WJ, SL6WT, SL6Z5) |
| Frequency (MHz) ? | 2800 |
| Bus speed (MHz) ? | 800 |
| Clock multiplier ? | 14 |
| Package | 478-pin Flip-Chip Pin Grid Array (FC-PGA2) |
| Socket | Socket 478 (mPGA478B) |
| Introduction date | May 21, 2003 |
| Architecture / Microarchitecture | |
| Processor core ? | Northwood |
| Core steppings ? | D1 (QWA5, QWP6ES, SL6WJ, SL6WT, SL78Y) M0 (SL6Z5) |
| Manufacturing process | 0.13 micron CMOS technology 55 million transistors |
| Data width | 32 bit |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | Approximately 12K micro-ops execution trace cache 8 KB data cache |
| Level 2 cache size ? | 512 KB 8-way associative full-speed on-die cache |
| Features |
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| Low power features |
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| Electrical/Thermal parameters | |
| V core (V) ? | 1.475 - 1.525 |
| Minimum/Maximum operating temperature (°C) ? | 5 - 75 |
| Maximum power dissipation (W) ? | 79.32 (1.525V core) |
| Thermal Design Power (W) ? | 69.7 |
| Notes on Intel RK80532PG072512 | |
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CPU ID
NOTE: CPU ID information below was taken from one CPU and may include features that are not present in all different steppings of the Intel Pentium 4 2.80 GHz CPU.
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| General information | |
|---|---|
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Pentium(R) 4 CPU 2.80GHz |
| Cores: | 1 |
| Logical processors: | 2 |
| Processor type: | Original OEM Processor |
| CPUID signature: | F29 |
| Family: | 15 (0Fh) |
| Model: | 2 (02h) |
| Stepping: | 9 (09h) |
| TLB/Cache details: | Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 entries No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache |
| Cache: | L1 data | L1 instruction | L2 |
|---|---|---|---|
| Size: | 8 KB | 12K uops | 512 KB |
| Associativity: | 4-way set associative |
8-way set associative |
8-way set associative |
| Line size: | 64 bytes | 64 bytes | |
| Comments: | sectored cache | sectored cache |
| Instruction set extensions | Additonal instructions | ||
|---|---|---|---|
| MMX | CLFLUSH | ||
| SSE | CMOV | ||
| SSE2 | CMPXCHG8B | ||
| FXSAVE/FXRSTORE | |||
| SYSENTER/SYSEXIT | |||
| Major features | Other features | ||
| On-chip Floating Point Unit | 36-bit page-size extensions | ||
| Hyper-Threading Technology | Advanced programmable interrupt controller | ||
| Debug store | |||
| Debugging extensions | |||
| L1 context ID | |||
| Machine check architecture | |||
| Machine check exception | |||
| Memory-type range registers | |||
| Model-specific registers | |||
| Page attribute table | |||
| Page global extension | |||
| Page-size extensions (4MB pages) | |||
| Pending break enable | |||
| Physical address extensions | |||
| Self-snoop | |||
| Thermal monitor | |||
| Thermal monitor and software controlled clock facilities | |||
| Time stamp counter | |||
| Virtual 8086-mode enhancements | |||
| xTPR Update Control | |||
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