CPU Information
Traditionally, the Pentium brand has always been associated with high-performance desktop processors. Starting from the Pentium Dual-Core family, the brand was "downgraded" to medium-performance and medium-priced processors. During its introduction, in May 2007, the family was positioned between Core 2 Duo family and
single-core Celeron 400 series family. First two members of family were E2140 and E2160. Both processors had 1 MB level 2 cache - 2 or 4 times smaller than the level 2 cache on Core 2 Duo processors, but 2 times larger than the L2 cache on Celeron 400 series CPUs. Processor's frequency and Front Side Bus frequency was comparable to those frequencies of Celeron 4xx and the slowest Core 2 Duo processors.
| General information |
| Type | CPU / Microprocessor |
| Family | Intel Pentium Dual-Core |
| Model number ? | E2140 |
| CPU part number | HH80557PG0251M (SLA3J, SLA93, SLALS) |
| Box part numbers | BX80557E2140 (SLA3J, SLA93)
BXC80557E2140 (SLA3J, SLA93) |
| Frequency (MHz) ? | 1600 |
| Bus speed (MHz) ? | 800 |
| Clock multiplier ? | 8 |
| Package | 775-pin Flip Chip Land Grid Array (FC-LGA6)
1.48" x 1.48" (3.75 cm x 3.75 cm) |
| Socket | Socket 775 (LGA775) |
| Introduction date | May 2007 |
| |
| Architecture / Microarchitecture |
| Processor core | Allendale |
| Core steppings | G0 (SLALS)
L2 (SLA3J)
M0 (SLA93) |
| Manufacturing process | 0.065 micron |
| Data width | 64 bit |
| Number of cores | 2 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 2 x 32 KB instruction caches
2 x 32 KB data caches |
| Level 2 cache size ? | shared 1 MB |
| Features | - MMX instruction set
- SSE
- SSE2
- SSE3
- Supplemental SSE3
- EM64T technology ?
- Execute Disable Bit ?
|
| Low power features | - Halt mode
- Extended Halt mode
- Stop Grant mode ?
- Enhanced SpeedStep technology ?
|
| |
| Electrical/Thermal parameters |
| V core (V) ? | 0.85 - 1.5 |
| Minimum/Maximum operating temperature (°C) ? | 5 - 61.4 (Stepping L2, CPUID 6F2h)
5 - 73.3 (Stepping M0, CPUID 6FDh) |
| Minimum/Maximum power dissipation (W) ? | 8 (TDP for Enhanced HALT mode) / 111.15 |
| Thermal Design Power (W) ? | 65 |
| |
| Notes on Intel HH80557PG0251M |
- Actual bus frequency is 200 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 800 MHz
- BXC80557E2140 is a Chinese version
|
CPU ID
NOTE: CPU ID information below was taken from one CPU and
may include features that are not present in all different steppings of the
Intel Pentium Dual-Core E2140 CPU.
| Manufacturer: | Intel |
| Family: | Pentium Dual-Core |
| Processor Number: | E2140 |
|
| Part number: | HH80557PG0251M |
| S-Spec / Comment: | SLA93 |
| Submitted by: | CPU-World |
|
| General information |
|---|
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Pentium(R) Dual CPU E2140 @ 1.60GHz |
| Cores: | 2 |
| Logical processors: | 2 |
| Processor type: | Original OEM Processor |
| CPUID signature: | 6FD |
| Family: | 6 (06h) |
| Model: | 15 (0Fh) |
| Stepping: | 13 (0Dh) |
| TLB/Cache details: | 64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
| Cache: |
L1 data |
L1 instruction |
L2 |
|---|
| Size: |
32 KB |
32 KB |
1 MB |
| Associativity: |
8-way set
associative |
8-way set
associative |
4-way set
associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
| |
| Instruction set extensions | Additonal instructions |
|---|
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
| |
MONITOR/MWAIT |
| |
SYSENTER/SYSEXIT |
| |
| Major features | Other features |
|---|
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| Enhanced SpeedStep |
Advanced programmable interrupt controller |
| |
CPL qualified debug store |
| |
Debug store |
| |
Debugging extensions |
| |
LAHF/SAHF support in 64-bit mode |
| |
Machine check architecture |
| |
Machine check exception |
| |
Memory-type range registers |
| |
Model-specific registers |
| |
Page attribute table |
| |
Page global extension |
| |
Page-size extensions (4MB pages) |
| |
Pending break enable |
| |
Perfmon and Debug capability |
| |
Physical address extensions |
| |
Self-snoop |
| |
Thermal monitor |
| |
Thermal monitor and software controlled clock facilities |
| |
Time stamp counter |
| |
Virtual 8086-mode enhancements |
| |
xTPR Update Control |
