| General information |
| Type | CPU / Microprocessor |
| Family | Intel A100 Series |
| Model number ? | A110 |
| CPU part number | UM80536UC800512 (QSEJ, SLAWA) |
| Frequency (MHz) ? | 800 |
| Bus speed (MHz) ? | 400 |
| Clock multiplier ? | 8 |
| Package | 663-ball micro-FCBGA
0.55" x 0.75" (14 mm x 19 mm) |
| Introduction date | Apr 18, 2007 |
| |
| Architecture / Microarchitecture |
| Processor core | Stealey |
| Core stepping | C0 (QSEJ) |
| Manufacturing process | 0.09 micron |
| Data width | 32 bit |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 32 KB instruction cache
32 KB write-back data cache |
| Level 2 cache size ? | 512 KB |
| Features | - MMX technology
- SSE
- SSE2
- Execute disable bit ?
|
| Low power features | - AutoHALT mode ?
- Stop Grant mode ?
- Sleep mode ?
- Deep Sleep mode ?
- Deeper Sleep mode ?
- Dynamic FSB power down
- Enhanced SpeedStep technology ?
|
| |
| Electrical/Thermal parameters |
| V core (V) ? | 0.796 - 0.94 |
| Minimum/Maximum operating temperature (°C) ? | 0 - 100 |
| Minimum/Maximum power dissipation (W) ? | 2.73 (Deeper Sleep mode) / 7.35 |
| Thermal Design Power (W) ? | 3 |
| |
| Notes on Intel UM80536UC800512 |
- Bus frequency is 100 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 400 MHz
|
