MIPS R3000 is a 32-bit microprocessor that implements MIPS 1
instruction set architecture. MIPS 1 instruction set is very small as
compared to instruction sets of other (80x86, 680x0, etc)
microprocessors, as it includes only most commonly used instructions
and supports very limited number of addressing modes. Small number of
CPU instructions, as well as other instruction set features - fixed
instruction length and only three different types of instruction
formats - greatly simplify instruction decoding and processing. To
speed-up processing even further the CPU employs 5-stage pipeline.
Very efficient pipeline design allows the R3000 CPU execute most
instructions at a rate close to 1 instruction per cycle.
In addition to the CPU core, the R3000 microprocessor includes
Control Processor (CP), that contains Translation Lookaside Buffer
and Memory Management Unit. The CP works as a co-processor. Besides
the CP, the R3000 can also support external
R3010 numeric co-processor and two
other external co-processors.
The R3000 CPU does not include its own level 1 cache. Instead, the
processor has on-chip Cache controller which controls separate
external data and instruction caches. The size of each external cache
can be as large as 256 KB. The CPU can access both caches during the
same CPU cycle.
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