NEC D30401RJ-50 (VR4000SC-50)

Specifications

General information
Type	CPU / Microprocessor
Frequency ?	50 MHz
Clock multiplier ?	2, 3 or 4
Package	447-pin staggered ceramic PGA

Architecture / Microarchitecture
Manufacturing process	1.3 million transistors
Data width	64 bit
Floating Point Unit	Integrated
Level 1 cache size ?	8 KB direct-mapped code cache, can be expanded to 32 KB 8 KB direct-mapped write-back data cache, can be expanded to 32 KB
Level 2 cache size ?	External 128 KB - 4 MB
Physical memory	64 GB
Virtual memory	2 GB (32-bit mode); 1 TB (64-bit mode)
Pipeline	8 stages
On-chip peripherals	128-bit secondary cache bus interface System control coprocessor Memory management unit

Notes
Internal pipeline operates at 100 MHz.

Last modified: 19 Mar 2013