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NEC D30401RJ-50 (VR4000SC-50)

 Information

NEC D30401RJ-50 (VR4000SC-50)
 History

 Architecture

 Identification

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TypeMicroprocessor
Manufacturing process1.3 million transistors
Data bus width64 bit
Package447-pin staggered ceramic PGA
Speed (MHz)50
Clock multiplier2, 3 or 4
On-chip peripherals
  • 128-bit secondary cache bus interface
  • System control coprocessor
  • Memory management unit
    Physical memory (GB)64
    Virtual memory2 GB (32-bit mode); 1 TB (64-bit mode)
    Level 1 cache size8 KB direct-mapped code cache, can be expanded to 32 KB
    8 KB direct-mapped write-back data cache, can be expanded to 32 KB
    Level 2 cache sizeExternal 128 KB - 4 MB
    Floating Point UnitIntegrated

    Notes:
    • Internal pipeline operates at 100 MHz.
    Comments: 0Add comment
    Last modified: 2 Dec 2005 

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    (c) Copyright 2003 Gennadiy Shvets