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| Type | Microprocessor |
| Manufacturing process | 1.3 million transistors |
| Data bus width | 64 bit |
| Package | 447-pin staggered ceramic PGA |
| Speed (MHz) | 50 |
| Clock multiplier | 2, 3 or 4 |
| On-chip peripherals |
- 128-bit secondary cache bus interface
- System control coprocessor
- Memory management unit
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| Physical memory (GB) | 64 |
| Virtual memory | 2 GB (32-bit mode); 1 TB (64-bit mode) |
| Level 1 cache size | 8 KB direct-mapped code cache, can be expanded to 32 KB
8 KB direct-mapped write-back data cache, can be expanded to 32 KB |
| Level 2 cache size | External 128 KB - 4 MB |
| Floating Point Unit | Integrated |
Notes:- Internal pipeline operates at 100 MHz.
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